Editing Design rule checking (section)

==Software==
The main objective of design rule checking (DRC) is to achieve a high overall yield and reliability for the design. If design rules are violated the design may not be functional. To meet this goal of improving die yields, DRC has evolved from simple measurement and Boolean checks, to more involved rules that modify existing features, insert new features, and check the entire design for process limitations such as layer density. A completed layout consists not only of the geometric representation of the design, but also data that provides support for the manufacture of the design. While design rule checks do not validate that the design will operate correctly, they are constructed to verify that the structure meets the process constraints for a given design type and process technology.

DRC software usually takes as input a layout in the [[GDSII]] standard format and a list of rules specific to the semiconductor process chosen for fabrication. From these it produces a report of design rule violations that the designer may or may not choose to correct. Carefully "stretching" or waiving certain design rules is often used to increase performance and component density at the expense of yield.

DRC products define rules in a [[computer language|language]] to describe the operations needed to be performed in DRC. For example, Mentor Graphics uses ''Standard Verification Rule Format'' (SVRF) language in their DRC rules files and Magma Design Automation is using [[Tcl]]-based language.<ref>{{Cite web |title=Mguide Automation Using SVRF Coding and Bash Scripting |url=https://scholar.google.com/citations?view_op=view_citation&hl=en&user=GXghZfgAAAAJ&sortby=pubdate&citation_for_view=GXghZfgAAAAJ:URGbnSt0D2cC |access-date=2024-02-26 |website=scholar.google.com}}</ref> A set of rules for a particular process is referred to as a run-set, rule deck, or just a deck.

DRC is a very computationally intense task.<ref>{{Cite web |title=Enhanced Design For Manufacturing Analysis using Python & TCL coding |url=https://scholar.google.com/citations?view_op=view_citation&hl=en&user=GXghZfgAAAAJ&sortby=pubdate&citation_for_view=GXghZfgAAAAJ:ZZwcLRaXOV4C |access-date=2024-02-26 |website=scholar.google.com}}</ref> Usually DRC checks will be run on each sub-section of the ASIC to minimize the number of errors that are detected at the top level. If run on a single CPU, customers may have to wait up to a week to get the result of a Design Rule check for modern designs. Most design companies require DRC to run in less than a day to achieve reasonable cycle times since the DRC will likely be run several times prior to design completion. With today's processing power, full-chip DRCs may run in much shorter times as quick as one hour depending on the chip complexity and size.

Some categories of design rules (checked by DRC) in IC design include:
*Active to active spacing
*Well to well spacing
*Minimum channel length of the transistor
*Minimum metal width
*Metal to metal spacing
*Metal fill density (for processes using CMP)
*Poly density
*ESD and I/O rules
*[[Antenna effect]]

===Commercial===
Major products in the ''DRC'' area of ''EDA'' include:

* ''[[Altium Designer]]''
* ''[[Advanced Design System]] Desktop DRC'' by [[PathWave Design]] ([[Keysight Technologies]] Previously [[Agilent]]'s [[EEsof]] EDA division)
* ''Calibre'' by [[Mentor Graphics]]
* ''Diva'', ''DRACULA'', ''Assura'', ''PVS'' and ''Pegasus'' by [[Cadence Design Systems]]
* ''Hercules'' and ''IC Validator'' by [[Synopsys]]
* ''Guardian'' by [[Silvaco]]
* ''HyperLynx DRC Free/Gold'' by Mentor Graphics
* ''PowerDRC'' -now SmartDRC by Silvaco
* ''SmartDRC'' by Silvaco
* ''Quartz'' by [[Magma Design Automation]]

===Free software===
* ''[[Electric (software)|Electric VLSI Design System]]''
* ''KLayout''
* ''[[Magic (software)|Magic]]''
* '' Alliance -- A Free VLSI/CAD System''
* Opencircuitdesign software:
* ''Microwind -- An educational layout CAD system''
* '' Opensource 130nm CMOS PDK by Google and SkyWater tech. Foundry''