Editing Direct digital synthesis (section)

== Performance ==
A DDS has many advantages over its analog counterpart, the [[phase-locked loop]] (PLL), including much better frequency agility, improved [[phase noise]], and precise control of the output phase across frequency switching transitions. Disadvantages include spurious responses mainly due to truncation effects in the [[Numerically controlled oscillator|NCO]], crossing spurs resulting from high order (>1) Nyquist images, and a higher noise floor at large frequency offsets due mainly to the [[digital-to-analog converter]].<ref name="AD DDSvPLL"/>

Because a DDS is a [[Nyquist–Shannon sampling theorem|sampled system]], in addition to the desired waveform at output frequency F<sub>out</sub>, [[Nyquist frequency|Nyquist images]] are also generated (the primary image is at F<sub>clk</sub>-F<sub>out</sub>, where F<sub>clk</sub> is the reference clock frequency). In order to reject these undesired images, a DDS is generally used in conjunction with an analog [[reconstruction filter|reconstruction lowpass filter]] as shown in Figure 1.<ref>Kroupa, Venceslav F.,''Direct Digital Frequency Synthesizers'', IEEE Press, 1999, {{ISBN|0-7803-3438-8}}</ref>

=== Frequency agility ===
The output frequency of a DDS is determined by the value stored in the frequency control register (FCR) (see Fig.1), which in turn controls the [[Numerically controlled oscillator|NCO]]'s phase accumulator step size. Because the NCO operates in the discrete-time domain, it changes frequency instantaneously at the clock edge coincident with a change in the value stored in the FCR. The DDS output frequency settling time is determined mainly by the phase response of the reconstruction filter. An ideal reconstruction filter with a linear phase response (meaning the output is simply a delayed version of the input signal) would allow instantaneous frequency response at its output because a linear system can not create frequencies not present at its input.<ref name="Chen"/>

=== Phase noise and jitter ===

The superior close-in [[phase noise]] performance of a DDS stems from the fact that it is a feed-forward system. In a traditional [[phase locked loop]] (PLL), the [[frequency divider]] in the feedback path acts to multiply the phase noise of the reference oscillator and, within the PLL loop bandwidth, impresses this excess noise onto the VCO output. A DDS, on the other hand, reduces the reference clock phase noise by the ratio <math>f_{clk}/f_o</math> because the fractional division of the clock derives its output. Reference clock [[jitter]] translates directly to the output, but this jitter is a smaller percentage of the output period (by the ratio above). Since the maximum output frequency is limited to <math>f_{clk}/2</math>, the output phase noise at close-in offsets is always at least 6&nbsp;dB below the reference clock phase noise.<ref name="AD DDSvPLL"/>

At offsets far removed from the carrier, the phase-noise floor of a DDS is determined by the power sum of the DAC [[Quantization (signal processing)|quantization]] noise floor and the reference clock phase noise floor.