Editing Display Data Channel (section)

==Physical link==
Prior to the DDC, the [[VGA]] standard had reserved four pins in the analog [[VGA connector]], known as ID0, ID1, ID2 and ID3 (pins 11, 12, 4 and 15) for identification of monitor type. These ID pins, attached to resistors to pull one or more of them to ground (GND), allowed for the definition of the monitor type, with all open (n/c, not connected) meaning "no monitor".

In the most commonly documented scheme, the ID3 pin was unused and only the 3 remaining pins were defined. The ID0 was pulled to GND by color monitors, while the monochrome monitors pulled ID1 to GND. Finally, the ID2 pulled to GND signaled a monitor capable of 1024×768 resolution, such as [[IBM 8514]]. In this scheme, the input states of the ID pins would encode the monitor type as follows:<ref>{{Cite web|url=https://patents.google.com/patent/US5285197/en|title=Method and apparatus for automatic selection of scan rates for enhanced VGA-compatible monitors}}</ref><ref>[http://www.cs.nyu.edu/~mwalfish/classes/15sp/ref/hardware/vgadoc/PINOUT.TXT Monitor Pinouts]</ref><ref>{{Cite web|url=https://pinoutguide.com/Video/VGA15_pinout.shtml|title=VGA pinout diagram @ pinoutguide.com|website=pinoutguide.com}}</ref>

{| class="wikitable"
! ID2 (pin 4) || ID0 (pin 11) || ID1 (pin 12) || monitor type
|-
| n/c || n/c || n/c || no monitor connected
|-
| n/c || n/c || GND || < 1024×768, monochrome
|-
| n/c || GND || n/c || < 1024×768, color
|-
| GND || GND|| n/c|| ≥ 1024×768, color
|}

More elaborate schemes also existed that used all of the 4 ID pins while manipulating the HSync and VSync signals in order to extract 16 bits (4 ID pin values for each of the 4 combinations of HSync and VSync states) of monitor identification.<ref>{{Cite web|url=http://archive.org/details/bitsavers_ibmpccardseferenceManualMay92_1756350|title=ibm :: pc :: cards :: IBM VGA XGA Technical Reference Manual May92|date=May 25, 1992|via=Internet Archive}}</ref>

DDC changed the purpose of the ID pins to incorporate a [[Serial communication|serial link interface]]. However, during the transition, the change was not backwards-compatible and video cards using the old scheme could have problems if a DDC-capable monitor was connected.<ref>[ftp://ftp.cis.nctu.edu.tw/pub/csie/Software/X11/private/VeSaSpEcS/VESA_Document_Center_Monitor_Interface/EDDCv1r1.pdf Enhanced Display Data Channel Standard, Version 1.1]{{dead link|date=May 2025|bot=medic}}{{cbignore|bot=medic}}</ref><ref>{{Cite web|url=https://www.eevblog.com/forum/projects/i2c-over-cat5e-problem/?action=dlattach;attach=185318|format=PDF|title=Enhanced Display Data Channel Standard, Version 1.1|date=March 24, 2004|access-date=2023-05-04|archive-url=https://web.archive.org/web/20230504201124/https://www.eevblog.com/forum/projects/i2c-over-cat5e-problem/?action=dlattach;attach=185318|archive-date=2023-05-04|url-status=live}}</ref> The DDC signal can be sent to or from a video graphics array (VGA) monitor with the I<sup>2</sup>C protocol using the master's serial clock and serial data pins.

===DDC1===
DDC1 is a simple, low-speed, unidirectional [[serial communications|serial link]] protocol. Pin 12, ID1 functions as a data line that continuously transmits the 128-byte EDID block, and the data clock is synchronised with [[vertical sync]], providing typical clock rates of 60 to 100&nbsp;Hz.

Very few display devices implemented this protocol.

=== DDC2 {{anchor|DDC2B}} ===
The most common version, called '''DDC2B''', is based on [[I²C]], a [[Serial communications|serial bus]]. Pin 12, ID1, of the VGA connector is used as the data pin of the I²C bus, and the formerly-unused pin 15 is the I²C clock. Pin 9, previously used as a mechanical key, supplies +5V DC power (up to 50mA) to power the EEPROM. With this, the host can read the EDID even if the monitor is powered off. Though I²C is fully [[Two-way communication|bidirectional]] and supports multiple [[Bus mastering|bus-masters]], DDC2B is unidirectional and allows only one [[Bus mastering|bus master]]—the graphics adapter. The monitor acts as a slave device at the 7-bit I²C address 50h, and provides 128-256 bytes of read-only EDID. Because this access is always a read, the first I²C octet will always be A1h.

{{anchor|DDC2Ab}}
'''DDC2Ab''' is an implementation of the I²C-based 100-kbit/s [[ACCESS.bus]] interface, which made it possible for monitor manufacturers to support external ACCESS.bus peripherals such as a mouse or keyboard with little to no additional effort. Such devices and monitors were briefly available in the mid-1990s, but they disappeared with the introduction of [[Universal Serial Bus|USB]].

'''DDC2B+''' and '''DDC2Bi''' are scaled-down versions of DDC2Ab which only support monitor and graphics card devices but still allow bidirectional communication between them.

DDC2 is not exclusive to the VGA interface. Both [[Digital Visual Interface|DVI]] and [[High-Definition Multimedia Interface|HDMI]] feature dedicated DDC2B wires.