Editing Double data rate (section)

== Relation of bandwidth and frequency ==
Describing the bandwidth of a double-pumped bus can be confusing.  Each clock edge is referred to as a ''[[beat (music)|beat]]'', with two beats (one [[Beat (music)#Downbeat and upbeat|upbeat]] and one [[Beat (music)#Downbeat|downbeat]]) per cycle.  Technically, the [[hertz]] is a unit of ''cycles'' per second, but many people refer to the number of ''transfers'' per second.  Careful usage generally talks about "500&nbsp;MHz, double data rate" or "1000&nbsp;[[MT/s]]", but many refer casually to a "1000&nbsp;MHz bus," even though no signal cycles faster than 500&nbsp;MHz.

[[DDR SDRAM]] popularized the technique of referring to the bus bandwidth in [[megabytes per second]], the product of the transfer rate and the bus width in bytes.  DDR SDRAM operating with a 100&nbsp;MHz clock is called DDR-200 (after its 200&nbsp;MT/s data transfer rate), and a 64-bit (8-byte) wide [[DIMM]] operated at that data rate is called PC-1600, after its 1600&nbsp;MB/s peak (theoretical) bandwidth.  Likewise, 12.8&nbsp;GB/s transfer rate DDR3-1600 is called PC3-12800.

Some examples of popular designations of DDR modules:
{| class="wikitable"
|-
! Names !! Memory clock !! I/O bus clock !! [[Transfer (computing)|Transfer rate]] !! Theoretical bandwidth
|-
| DDR-200, PC-1600
| 100&nbsp;MHz <!--Divide by 2 for DDR1-->
| 100&nbsp;MHz
| 200 MT/s
| 1.6 GB/s
|-
| DDR-400, PC-3200
| 200&nbsp;MHz <!--Divide by 2 for DDR1-->
| 200&nbsp;MHz
| 400 MT/s
| 3.2 GB/s
|-bgcolor=white
| DDR2-800, PC2-6400
| 200&nbsp;MHz <!--Divide by 4 for DDR2-->
| 400&nbsp;MHz
| 800 MT/s
| 6.4 GB/s
|-
| DDR3-1600, PC3-12800
| 200&nbsp;MHz <!--Divide by 8 for DDR3-->
| 800&nbsp;MHz
| 1600 MT/s
| 12.8 GB/s
|-bgcolor=white
|DDR4-2400, PC4-19200
| 300&nbsp;MHz <!--DDR4 remains 8n prefetch, so divide by 8 for DDR4-->
| 1200&nbsp;MHz
| 2400 MT/s
| 19.2 GB/s
|-bgcolor=white
| DDR4-3200, PC4-25600
| 400&nbsp;MHz <!--DDR4 remains 8n prefetch, so divide by 8 for DDR4-->
| 1600&nbsp;MHz
| 3200 MT/s
| 25.6 GB/s
|-
|DDR5-4800, PC5-38400
| 300&nbsp;MHz <!--Divide by 16 for DDR5-->
| 2400&nbsp;MHz
| 4800 MT/s
| 38.4 GB/s <!--Using both buses; DDR5 provides two independent buses per DIMM-->
|-
| DDR5-6400, PC5-51200
| 400&nbsp;MHz
| 3200&nbsp;MHz
| 6400 MT/s
| 51.2 GB/s
|}

DDR SDRAM uses double-data-rate signalling only on the data lines. Address and control signals are still sent to the DRAM once per clock ''cycle'' (to be precise, on the rising edge of the clock), and timing parameters such as [[CAS latency]] are specified in clock cycles. Some less common DRAM interfaces, notably [[LPDDR2]], [[GDDR5]] and [[XDR DRAM]], send commands and addresses using double data rate.  [[DDR5]] uses two 7-bit double data rate command/address buses to each DIMM, where a [[Registered memory|registered]] clock driver chip converts to a 14-bit SDR bus to each memory chip.