Editing Emitter-coupled logic (section)

==Implementation==
[[Image:ECL structure 1000.jpg|right|thumb|350px|The picture represents a typical ECL circuit diagram based on Motorola's MECL. In this schematic, transistor T5′ represents the output transistor of a previous ECL gate that provides a logic signal to input transistor T1 of an OR/NOR gate whose other input is at T2 and has outputs Y and {{overline|Y}}. Additional pictures illustrate the circuit operation by visualizing the voltage relief and current topology at [[:Image:ECL logical0 1000.jpg|low input voltage]] (logical "0"), [[:Image:ECL transition 1000.jpg|during the transition]] and at [[:Image:ECL logical1 1000.jpg|high input voltage]] (logical "1").]]

ECL is based on an emitter-coupled ([[Differential amplifier#Long-tailed pair|long-tailed]]) pair, shaded red in the figure on the right. The left half of the pair (shaded yellow) consists of two parallel-connected input transistors T1 and T2 (an exemplary two-input gate is considered) implementing NOR logic. The base voltage of the right transistor T3 is held fixed by a reference voltage source, shaded light green: the voltage divider with a diode thermal compensation (R1, R2, D1 and D2) and sometimes a buffering emitter follower (not shown on the picture); thus the emitter voltages are kept relatively steady. As a result, the common emitter resistor R<sub>E</sub> acts nearly as a [[current source]]. The output voltages at the collector load resistors R<sub>C1</sub> and R<sub>C3</sub> are shifted and buffered to the inverting and non-inverting outputs by the emitter followers T4 and T5 (shaded blue). The output emitter resistors R<sub>E4</sub> and R<sub>E5</sub> do not exist in all versions of ECL. In some cases 50&nbsp;Ω line termination resistors connected between the bases of the input transistors and −2&nbsp;V of a driven gate act as emitter resistors of the driving gate.<ref>{{harvnb|Blood Jr.|1972|p=3}}</ref>