Editing Emotion Engine (section)

=== CPU core ===
The CPU core is a two-way [[superscalar]] [[Out-of-order execution#In-order processors|in-order]] [[RISC]] processor.<ref>{{Cite newsletter|url=https://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/emotionengine%20(mpr).pdf|title=Sony's Emotionally Charged Chip|last=Diefendorff|first=Keith|date=19 April 1999|magazine=[[Microprocessor Report]]|access-date=1 September 2017|issue=5|volume=13|archive-url=https://web.archive.org/web/20180725122827/https://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/emotionengine%20(mpr).pdf|archive-date=25 July 2018|url-status=live}}</ref> Based on the MIPS R5900, it implements the [[MIPS architecture|MIPS-III]] [[instruction set architecture]] (ISA) and much of MIPS-IV, in addition to a custom instruction set developed by Sony which operated on 128-bit wide groups of either 32-bit, 16-bit, or 8-bit integers in [[single instruction, multiple data]] (SIMD) fashion (e.g. four 32-bit integers could be added to four others using a single instruction). Instructions defined include: add, subtract, multiply, divide, min/max, shift, logical, leading-zero count, 128-bit load/store and 256-bit to 128-bit funnel shift in addition to some not described by Sony for competitive reasons. Contrary to some misconceptions, these SIMD capabilities did not amount to the processor being "128-bit", as neither the memory addresses nor the integers themselves were 128-bit, only the shared SIMD/integer registers. For comparison, 128-bit wide registers and SIMD instructions had been present in the 32-bit [[x86]] architecture since 1999, with the introduction of [[Streaming SIMD Extensions|SSE]]. However the internal data paths were 128-bit wide, and its processors were capable of operating on 4x32bit quantities in parallel in single registers.

It has a 6-stage integer [[pipeline (computing)|pipeline]] and a 15-stage [[floating-point]] (FP) pipeline. Its assortment of registers consists of 32 128-bit VLIW SIMD registers (naming/renaming), one 64-bit accumulator and two 64-bit general data registers, 8 16-bit fix function registers, 16 8-bit controller registers. The processor also has two 64-bit integer [[arithmetic logic unit]]s (ALUs), a 128-bit [[load–store unit]] (LSU), a Branch Execution Unit (BXU), and a 32-bit VU1 [[floating-point unit]] (FPU) coprocessor (which acted as a sync controller for the VPU0/VPU1) containing a MIPS base processor core with 32 64-bit FP registers and 15 32-bit integer registers. The ALUs are 64-bit, with a 32-bit FPU that isn't IEEE 754 compliant. The custom instruction set 107 MMI (Multimedia Extensions) was implemented by grouping the two 64-bit integer ALUs. Both the integer and floating-point pipelines are six stages long.

To feed the execution units with instructions and data, there is a 16&nbsp;KB two-way set [[Associative cache|associative]] [[instruction cache]], an 8&nbsp;KB<ref name=prefix1>{{BDprefix|p=b}}</ref> two-way set associative non blocking data cache and a 16&nbsp;KB [[scratchpad RAM]]. Both the instruction and data caches are virtually indexed and physically tagged while the [[scratchpad RAM]] exists in a separate memory space. A combined 48 double entry instruction and data [[translation lookaside buffer]] is provided for translating [[virtual addressing|virtual addresses]]. [[Branch prediction]] is achieved by a 64-entry branch target address cache and a [[branch history table]] that is integrated into the instruction cache. The branch misprediction penalty is three cycles due to the short six stage pipeline.