Editing Fin field-effect transistor (section)

==Commercialization==
The industry's first 25 nanometer transistor operating on just 0.7 [[volt]]s was demonstrated in December 2002 by [[Taiwan Semiconductor Manufacturing Company|TSMC]]. The "Omega FinFET" design, named after the similarity between the Greek letter "[[Omega]]" and the shape in which the gate wraps around the source/drain structure, has a [[gate delay]] of just 0.39 [[picosecond]] (ps) for the N-type transistor and 0.88 ps for the P-type.

In 2004, [[Samsung]] demonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamic [[random-access memory]] ([[Dynamic random-access memory|DRAM]]) manufactured with a [[90 nanometer|90{{nbsp}}nm]] Bulk FinFET process.<ref name="Liu"/>

In 2011, [[Intel]] demonstrated [[tri-gate transistor]]s, where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors.<ref>{{Cite web|url=http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf|title=Intel's Revolutionary 22 nm Transistor Technology|last1=Bohr|first1=Mark|last2=Mistry|first2=Kaizad|date=May 2011|website=intel.com|access-date=April 18, 2018}}</ref><ref>{{Cite news|url=https://www.techradar.com/news/computing-components/processors/intel-s-tri-gate-transistors-everything-you-need-to-know-952572|title=Intel's Tri-Gate transistors: everything you need to know|last=Grabham|first=Dan|date=May 6, 2011|work=TechRadar|access-date=April 19, 2018}}</ref><ref>
{{cite journal |doi=10.1109/MM.2017.4241347|title=CMOS Scaling Trends and Beyond|journal=IEEE Micro|volume=37|issue=6|pages=20–29|year=2017|last1=Bohr|first1=Mark T.|last2=Young|first2=Ian A.
|s2cid=6700881|quote=The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel's 22-nm technology in 2011.}}
</ref>

Commercially produced chips at [[22 nm]] and below have generally utilised FinFET gate designs (but planar processes do exist down to 18&nbsp;nm, with 12&nbsp;nm in development). Intel's [[tri-gate]] variant were announced at 22&nbsp;nm in 2011 for its [[Ivy Bridge (microarchitecture)|Ivy Bridge microarchitecture]].<ref>{{Cite web|url=https://newsroom.intel.com/press-kits/intel-22nm-3-d-tri-gate-transistor-technology/|title=Intel 22nm 3-D Tri-Gate Transistor Technology|website=Intel Newsroom}}</ref> These devices shipped from 2012 onwards. From 2014 onwards, at [[14 nm]] (or 16&nbsp;nm) major foundries (TSMC, Samsung, [[GlobalFoundries]]) utilised FinFET designs.

In 2013, [[SK Hynix]] began commercial mass-production of a 16{{nbsp}}nm process,<ref name="hynix2010s">{{cite web |title=History: 2010s |url=https://www.skhynix.com/eng/about/history2010.jsp |website=[[SK Hynix]] |access-date=8 July 2019 |archive-date=17 May 2021 |archive-url=https://web.archive.org/web/20210517040328/https://www.skhynix.com/eng/about/history2010.jsp |url-status=dead }}</ref> TSMC began production of a 16{{nbsp}}nm FinFET process,<ref>{{cite web |title=16/12nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/16nm.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref> and [[Samsung Electronics]] began production of a [[10 nanometer|10{{nbsp}}nm]] process.<ref name="tomshardware">{{cite news |title=Samsung Mass Producing 128Gb 3-bit MLC NAND Flash |url=https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html |access-date=21 June 2019 |work=[[Tom's Hardware]] |date=11 April 2013 |archive-date=21 June 2019 |archive-url=https://web.archive.org/web/20190621175628/https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html |url-status=dead }}</ref> TSMC began production of a [[7&nbsp;nm]] process in 2017,<ref name="tsmc-7nm">{{cite web |title=7nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/7nm.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref> and Samsung began production of a [[5&nbsp;nm]] process in 2018.<ref>{{Cite web|url=https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology|title=Samsung Completes Development of 5nm EUV Process Technology|last=Shilov|first=Anton|website=www.anandtech.com|access-date=2019-05-31}}</ref> In 2019, Samsung announced plans for the commercial production of a 3{{nbsp}}nm [[GAAFET]] process by 2021.<ref>{{citation| url  =https://www.tomshardware.com/news/samsung-3nm-gaafet-production-2021,38426.html | title = Samsung Plans Mass Production of 3nm GAAFET Chips in 2021 | first = Lucian |last = Armasu | date = 11 January 2019| work = www.tomshardware.com }}</ref> FD-SOI (Fully Depleted [[silicon on insulator|Silicon On Insulator]]) has been seen as a potential low cost alternative to FinFETs.<ref>{{cite web | url=https://www.eetimes.com/samsung-gf-ramp-fd-soi/ | title=Samsung, GF Ramp FD-SOI | date=27 April 2018 }}</ref>

Commercial production of [[nanoelectronic]] FinFET [[semiconductor memory]] began in the 2010s.<ref name="auto"/> In 2013, SK Hynix began mass-production of 16{{nbsp}}nm [[NAND flash]] memory,<ref name="hynix2010s"/> and Samsung Electronics began production of [[10 nanometer|10{{nbsp}}nm]] [[multi-level cell]] (MLC) NAND flash memory.<ref name="tomshardware"/> In 2017, TSMC began production of [[Static random-access memory|SRAM]] memory using a 7&nbsp;nm process.<ref name="tsmc-7nm"/>