Editing Formal verification (section)

=== Model checking ===

[[Model checking]] involves a systematic and exhaustive exploration of the mathematical model. Such exploration is possible for [[Finite model theory|finite models]], but also for some infinite models, where infinite sets of states can be effectively represented finitely by using abstraction or taking advantage of symmetry. Usually, this consists of exploring all states and transitions in the model, by using smart and domain-specific abstraction techniques to consider whole groups of states in a single operation and reduce computing time. Implementation techniques include [[state space enumeration]], symbolic state space enumeration, [[abstract interpretation]], [[symbolic simulation]], abstraction refinement.{{citation needed|date=December 2014}} The properties to be verified are often described in [[temporal logic]]s, such as [[linear temporal logic]] (LTL), [[Property Specification Language]] (PSL), [[SystemVerilog]] Assertions (SVA),<ref>{{Cite book|title = SystemVerilog Assertions Handbook|edition = 4th |last1 = Cohen|first1 = Ben| first2=Srinivasan |last2 =Venkataramanan |first3=Ajeetha |last3 =Kumari |first4=Lisa |last4 =Piper | publisher = CreateSpace Independent Publishing Platform|year = 2015|isbn = 978-1518681448}}</ref> or [[computational tree logic]] (CTL). The great advantage of model checking is that it is often fully automatic; its primary disadvantage is that it does not in general scale to large systems; symbolic models are typically limited to a few hundred bits of state, while explicit state enumeration requires the state space being explored to be relatively small.