Editing Hybrid computer (section)

== VLSI hybrid computer chip ==
In 2015, researchers at Columbia University published a paper<ref>{{Cite book|date = 2015-09-01|pages = 279–282|doi = 10.1109/ESSCIRC.2015.7313881|first1 = Ning|last1 = Guo|first2 = Yipeng|last2 = Huang|first3 = Tao|last3 = Mai|first4 = S.|last4 = Patil|first5 = Chi|last5 = Cao|first6 = Mingoo|last6 = Seok|first7 = S.|last7 = Sethumadhavan|first8 = Y.|last8 = Tsividis| title=ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) | chapter=Continuous-time hybrid computation with programmable nonlinearities |isbn = 978-1-4673-7470-5| s2cid=16523767 }}</ref> on a small scale hybrid computer in 65&nbsp;nm CMOS technology. This 4th-order VLSI hybrid computer contains 4 integrator blocks, 8 multiplier/gain-setting blocks, 8 fanout blocks for distributing current-mode signals, 2 ADCs, 2 DACs and 2 SRAMs blocks. Digital controllers are also implemented on the chip for executing the external instructions. A robot experiment in the paper demonstrates the use of the hybrid computing chip in today's emerging low-power embedded applications.{{Citation needed|date=February 2025}}