Editing IBM ROMP (section)

==Architecture==
The ROMP's architecture was based on the original version of the [[IBM Research]] [[IBM 801|801]] [[minicomputer]]. The main differences were a larger [[word size]] (32 bits instead of 24), and the inclusion of [[virtual memory]].<ref>{{cite book |last1=Dewar |first1=Robert B.K. |last2=Smosna |first2=Matthew |title=Microprocessors: A Programmer's View |publisher=McGraw-Hill |page=378}}</ref> The architecture supported 8-, 16-, and 32-bit integers, 32-bit addressing, and a 40-bit [[virtual address space]]. It had an [[instruction pointer]] register and sixteen 32-bit [[general-purpose register]]s. The microprocessor was controlled by 118 simple 16- and 32-bit instructions.<ref name="Furber">{{cite book |last1=Furber |first1=Stephen |title=VLSI RISC Architecture and Organization |date=1989 |publisher=CRC Press |pages=106–109 |url=https://books.google.com/books?id=jKOsdJ8Rk6EC|isbn=9780824781514}}</ref>

The ROMP's virtual memory has a [[Memory segmentation|segmented]] 40-bit (1{{nbsp}}TB) address space consisting of 4,096 256{{nbsp}}MB segments. The 40-bit virtual address is formed in the MMU by [[Concatenation|concatenating]] a 12-bit segment identifier with 28 low-order bits from a 32-bit ROMP-computed virtual address. The segment identifier is obtained from a set of 16 segment identifiers stored in the MMU, addressed by the four high-order bits of the 32-bit ROMP-computed virtual address.<ref>{{cite book |last1=Tabak |first1=Daniel |title=RISC Architecture |date=1987 |publisher=Research Studies Press |pages=102–103}}</ref>