Editing IBM System/32 (section)

==Processor==

The System/32 featured a [[16-bit]] processor with a 200ns cycle time known as the ''Control Storage Processor'' (CSP).<ref name="henry-s32-museum">{{cite web|url=http://www.glennsmuseum.com/s32/s32.html|title=The IBM System/32: The Second IBM Personal Computer|website=Glenn's Computer Museum|date=2014-03-30|access-date=2021-12-22|author=[[Glenn Henry (IT entrepreneur)|Glenn Henry]]}}</ref> Whereas the System/3 used a hardwired processor, the System/32 implemented the System/3 instruction set in [[microcode]]. The System/32 processor utilized a vertical microcode format, with each microinstruction occupying 16 bits of control storage. There were 19 different microinstruction opcodes, however certain microinstructions could carry out different operations depending on which bits were set in the rest of the microinstruction, meaning that there were about 70 distinct operations available in total.<ref name="maintenance-library">{{cite web|url=http://www.bitsavers.org/pdf/ibm/system32/fe/SY31-0346-4_5320_Theory-Diagrams_Vol5_May77.pdf|title=IBM Maintenance Library System/32 Theory Diagrams|publisher=IBM|date=May 1977|access-date=2021-12-22|website=Bitsavers}}</ref> An optional set of ''Scientific Macroinstructions'' was also available, which were used to support a [[Fortran]] compiler by implementing support for [[floating point]] arithmetic in microcode.<ref name="scientific-instructions">{{cite web|url=http://www.bitsavers.org/pdf/ibm/system34/SA21-9275-0_IBM_System_34_and_System_32_Scientific_Microinstructions_Functions_Reference_Manual_1st_ed_197807.pdf|title=IBM System/34 and IBM System/32 Scientific Macroinstructions Functions Reference Manual|date=July 1978|publisher=IBM|access-date=2021-12-22|website=Bitsavers}}</ref> Some IBM engineers, including [[Glenn Henry (IT entrepreneur)|Glenn Henry]] and [[Frank Soltis]], have retrospectively described the System/32's microcode as resembling a [[RISC]] instruction set.<ref name="henry-s32-museum" /><ref name="inside-as400" />

The System/3 emulation performed poorly, which led IBM to implement performance critical parts of the SCP operating system directly in microcode.<ref name="henry-interview">{{cite interview|last=Henry|first=Glenn|interviewer=Philip L. Frana|title=An Interview with An Interview with GLENN HENRY|url=https://conservancy.umn.edu/bitstream/handle/11299/107623/oh381ds.pdf|publisher=Charles Babbage Institute|date=2001-08-07|website=conservancy.umn.edu|access-date=2021-12-22}}</ref> The later System/34 and System/36 systems addressed this problem by using two different processors - the System/32 CSP architecture was used exclusively for operating system, I/O control and floating point code, whereas user code ran on the ''Main Storage Processor'' (MSP) which implemented the System/3 instruction set directly in hardware without microcode.<ref name="inside-as400">{{cite book|title=Inside the AS/400, Second Edition|url=https://books.google.com/books?id=5DoPAAAACAAJ|isbn=978-1882419661|author=Frank G. Soltis|year=1997|publisher=Duke Press}}</ref> The use of microcode to implement instruction set emulation as well as performance-critical operating system components had some influence on the design of the microcode layers in the later [[System/38]].<ref name="henry-interview" />