Editing IBM System/4 Pi (section)

==Advanced Processor==
The '''AP-101''', being the top-of-the-line of the System/4 Pi range, shares its general architecture with the [[System/360]] [[IBM mainframe|mainframe]]s.<ref name=Tomayko1988 /> It is a repackaged version of the IBM Advanced Processor-1 (AP-1)<ref name=F15 /> used in the [[F-15 Eagle|F-15]] fighter.<ref name=Tomayko1988 /> The AP-1 prototypes were delivered in 1971 and the AP-101 in 1973.<ref name=IBM1981 /> It has 16 [[32-bit]] [[processor register|registers]].  Originally only 16 bits were available for addressing memory; later this was extended with four bits from the [[status register|program status word]] register, allowing a directly addressable memory range of 1[[Mega-|M]] locations. This [[avionics]] computer has been used in the U.S. [[Space Shuttle program|Space Shuttle]], the [[B-52 Stratofortress|B-52]] and [[B-1B]] bombers,<ref name=Tomayko1988 /> and other aircraft. It remained in service on the Space Shuttle because it worked, was flight-certified, and developing a new system would have been too expensive.<ref>{{cite web |first=Ben |last=Rossi |title=The shuttle: NASA's IT legacy |date=18 July 2011 |publisher=Information Age |url=https://www.information-age.com/the-shuttle-nasas-it-legacy-1641693/}}</ref>

There were a number of variants of the AP101. The Offensive Avionics System, a retrofit update of the B-52, contains two AP-101C computers.<ref>{{cite report |last=Gross |first=James P. |author-link= |date=February 1981 |title=Techniques for Interfacing Multiplex Systems |url=https://apps.dtic.mil/sti/pdfs/ADA101457.pdf |publisher=Air Force Systems Command |page= |docket= |access-date= |quote=}}</ref> The AP-101C prototypes were delivered in 1978.<ref name=IBM1981 /> The B-1B employs a network of eight model AP-101F computers.<ref>{{cite book |last1=Stormont |first1=D.P. |last2=Welgan |first2=R. |title=Proceedings of National Aerospace and Electronics Conference (NAECON'94) |chapter=Risk management for the B-1B computer upgrade |date=23–27 May 1994 |chapter-url= https://zenodo.org/record/1232223|volume=2 |pages=1143–1149 |doi=10.1109/NAECON.1994.332913 |isbn=0-7803-1893-5 |s2cid=109575632 }}<!--|access-date=23 October 2013--></ref> The Space Shuttle used two variants of the AP-101: the earlier AP-101B and the upgraded AP-101S. The AP-101B was used for a series of [[Approach and Landing Tests]] in 1977. The [[STS-1|first ascent to orbit]] was in 1981. The AP-101S [[STS-101|first launched in 2000]].

[[File:IBM AP-101S logic board.jpg|thumb|Logic board from an IBM AP-101S Space Shuttle General Purpose Computer.]] Each AP-101 on the Shuttle was coupled with an [[I/O processor|input-output processor]] (IOP), consisting of one Master Sequence Controller (MSC) and 24 Bus Control Elements (BCEs).  The MSC and BCEs executed programs from the same memory system as the main CPU, offloading control of the Shuttle's serial data bus system from the CPU. The AP-101B originally used in the Space Shuttle had [[magnetic-core memory]]. The upgrade to the AP-101S in the early 1990s replaced the core with [[semiconductor memory]] and reduced the size from two to one chassis.<ref name=AP101S /> It was augmented by [[glass cockpit]] technology. Both variants use a [[microprogram]] to define the [[instruction set]] architecture. The early AP-101 variants used IBM'S Multipurpose Midline Processor (MMP) architecture.<ref name=MMP /> The AP-101B microprogram implemented MMP with 154 instructions. The AP101S could operate with a backwards compatible MMP with 158 instructions or the [[MIL-STD-1750A]] architecture with 243 instructions.<ref name=AP101S /> It was based on the AP-101F used in the B-1B. The AP-101S/G was an interim processor. The AP-101B performance was 0.420 [[Instructions_per_second#Millions_of_instructions_per_second_(MIPS)|MIPS]], while the AP-101S was 1.27 MIPS.<ref name=AP101S /> James E. Tomayko, who was contracted by NASA to write a history of computers in spaceflight,  has said:<ref name=Tomayko1985 /> {{blockquote|text="It was available in basically its present form when NASA was specifying requirements for the shuttle contracts in the 1970s. As such, it represents the first manned spacecraft computer system with hardware intentionally behind the state of the art."}}

The Space Shuttle used five AP-101 computers as ''General-Purpose Computers'' (GPCs). Four operated in sync, for redundancy, while the fifth was a backup running software written independently. The Shuttle's [[guidance, navigation and control]] software was written in [[HAL/S]], a special-purpose [[high-level programming language]], while much of the operating system and low-level utility software was written in [[assembly language]]. AP-101s used by the [[US Air Force]] are mostly programmed in [[JOVIAL]], such as the system found on the B-1B bomber.<ref>[https://web.archive.org/web/20121012015607/http://business.highbeam.com/438317/article-1G1-3161147/jovial-smooth-us-air-force-shift-ada Jovial to smooth U.S. Air Force shift to Ada. (processing language)]</ref>

The AP-102 variant design began in 1984. It is a MIL-STD-1750A standard instruction set architecture. It was first used in the [[Lockheed F-117 Nighthawk|F-117A Nighthawk]]. It was upgraded to the AP-102A in the early 1990s.<ref name=AP102 />