Editing Instruction pipelining (section)

==={{Anchor|SUPER}}Number of steps===
The number of dependent steps varies with the machine architecture. For example:
* The 1956–61 [[IBM Stretch]] project proposed the terms Fetch, Decode, and Execute that have become common.
* The [[classic RISC pipeline]] comprises:
*# Instruction fetch
*# Instruction decode and register fetch
*# Execute
*# Memory access
*# Register write back
* The [[Atmel AVR]] and the [[PIC microcontroller]] each have a two-stage pipeline.
* Many designs include pipelines as long as 7, 10 and even 20 stages (as in the [[Intel]] [[Pentium 4]]).
* The later "Prescott" and "Cedar Mill" [[NetBurst]] cores from Intel, used in the last Pentium&nbsp;4 models and their [[Pentium D]] and [[Xeon]] derivatives, have a long 31-stage pipeline.
* The Xelerated X10q Network Processor has a pipeline more than a thousand stages long, although in this case 200 of these stages represent independent CPUs with individually programmed instructions. The remaining stages are used to coordinate accesses to memory and on-chip function units.<ref>{{cite journal|last1=Glaskowsky|first1=Peter|title=Xelerated's Xtraordinary NPU — World's First 40Gb/s Packet Processor Has 200 CPUs|journal=Microprocessor Report|date=Aug 18, 2003|volume=18|issue=8|pages=12–14|url=http://www.linleygroup.com/mpr/h/2003/0818/173301.html|access-date=20 March 2017}}</ref><ref>{{cite web | url=https://www.eetimes.com/xelerated-brings-programmable-40-gbits-s-technology-to-the-mainstream-ethernet/# | title=Xelerated Brings Programmable 40 Gbits/S Technology to the Mainstream Ethernet | date=31 May 2003 }}</ref>{{More citations needed|date=October 2020}}

As the pipeline is made "deeper" (with a greater number of dependent steps), a given step can be implemented with simpler circuitry, which may let the processor clock run faster.<ref name=Guardian>{{cite book |url=https://books.google.com/books?id=Nibfj2aXwLYC&q=deep%20pipeline%20processor&pg=PA94 |title=Modern Processor Design |author=John Paul Shen, Mikko H. Lipasti |year=2004 |publisher=[[McGraw-Hill Professional]]|isbn=9780070570641 }}</ref> Such pipelines may be called ''superpipelines.''<ref>{{cite book |url=https://books.google.com/books?id=xgtTAAAAMAAJ&q=%22a+superpipeline+is+essentially+a+deep+instruction+pipeline+with+many+stages%22 |title=Design of Computers and Other Complex Digital Devices |author=Sunggu Lee |year=2000 |publisher=[[Prentice Hall]]|isbn=9780130402677 }}</ref>

A processor is said to be ''fully pipelined'' if it can fetch an instruction on every cycle. Thus, if some instructions or conditions require delays that inhibit fetching new instructions, the processor is not fully pipelined.