Editing Intel i960 (section)

==Architecture==
The i960 family features four distinct architectures, designed for upward binary compatibility:
<ref name="80960xa">{{cite web |title=80960XA Embedded 32-bit Microprocessor with 33rd Tag Bit to Support Object-Oriented Programming and Data Security |url=http://www.bitsavers.org/components/intel/i960/271159-001_80960XA_Advance_Information_Oct90.pdf |publisher=Intel}}</ref>
* '''Core''' architecture is a RISC-like core
* '''Numerics''' architecture adds floating point
* '''Protected''' architecture adds paged memory management, supervisor/user protection, string instructions, process scheduling, interprocess communication for the OS, and symmetric multiprocessing
* '''Extended''' architecture adds object protection and interprocess communication for applications

In the initial release, the 80960KA supported the Core architecture, the 80960KB supported the Numerics architecture, the 80960MC supported the Protected architecture, and the 80960XA supported the Extended architecture.

To avoid the performance issues that plagued the i432, the central i960 instruction-set architecture was a RISC design. In the Extended architecture, the memory subsystem was 33-bits wide—to accommodate a 32-bit word and a "tag" bit to implement memory protection in hardware. In many ways, the i960 followed the original [[Berkeley RISC]] design, notably in its use of [[register window]]s, an implementation-specific number of caches for the per-subroutine registers that allowed for fast subroutine calls. The competing [[Stanford University]] design, [[Stanford MIPS|MIPS]], did not use this system, instead relying on the compiler to generate optimal subroutine call and return code. In common with most 32-bit designs, the i960 has a flat 32-bit memory space, with no [[segmented memory|memory segmentation]], except for the Extended architecture, which could support up to 2<sup>26</sup> "objects", each up to 2<sup>32</sup> bytes in size.<ref>{{cite book|url=http://bitsavers.org/pdf/biin/BiiN_CPU_Architecture_Reference_Man_Jul88.pdf|title=BiiN CPU Architecture Reference Manual|date=July 1998|publisher=BiiN}}</ref> The i960 architecture also anticipated a [[superscalar]] implementation, with instructions being simultaneously dispatched to more than one unit within the processor.