Editing Intel iAPX 432 (section)

==History==

==={{Anchor|8800}}Development===
Intel's 432 project started in 1976, a year after the [[8-bit]] [[Intel 8080]] was completed and a year before their 16-bit [[Intel 8086|8086]] project began. The 432 project was initially named the '''8800''',<ref name="i8800"/> as their next step beyond the existing [[Intel 8008]] and [[Intel 8080|8080]] microprocessors.  This became a very big step.  The instruction sets of these 8-bit processors were not very well fitted for typical [[ALGOL|Algol]]-like [[compiled language]]s. However, the major problem was their small native addressing ranges, just 16 KB for 8008 and 64 KB for 8080, far too small for many complex software systems without using some kind of [[bank switching]], [[memory segmentation]], or similar mechanism (which was built into the 8086, a few years later on).  Intel now aimed to build a sophisticated complete system in a few LSI chips, that was functionally equal to or better than the best 32-bit minicomputers and mainframes requiring entire cabinets of older chips.  This system would support multiprocessors, modular expansion, fault tolerance, advanced operating systems, advanced programming languages, very large applications, ultra reliability, and ultra security.  Its architecture would address the needs of Intel's customers for a decade.<ref>{{cite web|title=Intel iAPX 432 - Computer Science 460 - Final Project|author1=David King|author2=Liang Zhou|author3=Jon Bryson|author4=David Dickson|date=April 15, 1999|url=http://www.brouhaha.com/~eric/retrocomputing/intel/iapx432/cs460}}</ref>

The iAPX 432 development team was managed by Bill Lattin, with [[Justin Rattner]] (who would later become CTO of Intel) as the lead engineer<ref>{{cite journal |last1=Mazor |first1=Stanley |title=Intel's 8086 |journal=IEEE Annals of the History of Computing |date=2010 |volume=32 |page=75 |doi=10.1109/MAHC.2010.22 |s2cid=16451604 |url=https://ieeexplore.ieee.org/document/5430762|url-access=subscription }}</ref><ref name="Mayer2012"></ref><ref>{{cite book |title=Defining Intel: 25 years / 25 events |date=1993 |publisher=Intel |page=14 |url=https://www.intel.com/assets/pdf/general/25yrs.pdf}}</ref> (although one source<ref name="dvorak"/> states that [[Fred Pollack]] was the lead engineer). Initially the team worked from Santa Clara, but in March 1977 Lattin and his team of 17 engineers moved to Intel's new site in Portland.<ref name="Mayer2012">{{cite book|author=Heike Mayer|title=Entrepreneurship and Innovation in Second Tier Regions|url=https://books.google.com/books?id=OgUJJPuDvfQC&pg=PA100|year=2012|publisher=Edward Elgar Publishing|isbn=978-0-85793-869-5|pages=100–101}}</ref> Pollack later specialized in [[superscalar]]ity and became the lead architect of the i686 chip [[Intel Pentium Pro]].<ref name="dvorak"/>

It soon became clear that it would take several years and many engineers to design all this.  And it would similarly take several years of further progress in [[Moore's Law]], before improved [[Semiconductor device fabrication|chip manufacturing]] could fit all this into a few dense chips.  Meanwhile, Intel urgently needed a simpler interim product to meet the immediate competition from [[Motorola]], [[Zilog]], and [[National Semiconductor]]. So Intel began a rushed project to design the 8086 as a low-risk incremental evolution from the 8080, using a separate design team.  The mass-market 8086 shipped in 1978.

The 8086 was designed to be backward-compatible with the 8080 in the sense that 8080 [[assembly language]] could be mapped on to the 8086 architecture using a special [[assembler (computing)|assembler]]. Existing 8080 assembly [[source code]] (albeit no [[executable code]]) was thereby made [[upward compatible]] with the new 8086 to a degree. In contrast, the 432 had no software compatibility or migration requirements.  The architects had total freedom to do a novel design from scratch, using whatever techniques they guessed  would be best for large-scale systems and software.  They applied fashionable computer science concepts from universities, particularly [[capability-based addressing|capability machines]], object-oriented programming, high-level CISC machines, Ada, and densely encoded instructions.  This ambitious mix of novel features made the chip larger and more complex. The chip's complexity limited the clock speed and lengthened the design schedule.

The core of the design — the main processor — was termed the General Data Processor ('''GDP''') and built as two [[integrated circuit]]s: one (the 43201) to [[Fetch-execute cycle|fetch and decode]] instructions, the other (the 43202) to execute them. Most systems would also include the 43203 Interface Processor ('''IP''') which operated as a [[channel controller]] for [[Input/output|I/O]], and an Attached Processor ('''AP'''), a conventional Intel 8086 which provided "processing power in the I/O subsystem".<ref name=Intel81 />

These were some of the largest {{Clarify|IC|date=October 2012}} designs of the era. The two-chip GDP had a combined count of approximately 97,000&nbsp;[[transistor]]s{{Citation needed|reason=Another source states 159,000 transistors|date=April 2023}} while the single chip IP had approximately 49,000. By comparison, the [[Motorola 68000]] (introduced in 1979) had approximately 40,000&nbsp;transistors.{{Citation needed|reason=Other (unreliable) sources say the 68000 had about 70,000 transistors|date=September 2018}}

In 1983, Intel released two additional integrated circuits for the iAPX 432 Interconnect Architecture: the 43204 Bus Interface Unit ('''BIU''') and 43205 Memory Control Unit ('''MCU'''). These chips allowed for nearly glueless multiprocessor systems with up to 63&nbsp;nodes.

===The project's failures===
Some of the innovative features of the iAPX 432 were detrimental to good performance. In many cases, the iAPX 432 had a significantly slower instruction throughput than conventional microprocessors of the era, such as the [[National Semiconductor 32016]], [[Motorola 68010]] and [[Intel 80286]]. One problem was that the two-chip implementation of the GDP limited it to the speed of the motherboard's electrical wiring. A larger issue was the capability architecture needed large associative caches to run efficiently, but the chips had no room left for that. The instruction set also used bit-aligned variable-length instructions instead of the usual semi-fixed byte or word-aligned formats used in the majority of computer designs. Instruction decoding was therefore more complex than in other designs. Although this did not hamper performance in itself, it used additional transistors (mainly for a large [[barrel shifter]]) in a design that was already lacking space and transistors for caches, wider buses and other performance oriented features. In addition, the BIU was designed to support fault-tolerant systems, and in doing so up to 40% of the bus time was held up in [[wait state]]s.

Another major problem was its immature and untuned [[Ada (programming language)|Ada]] [[compiler]]. It used high-cost object-oriented instructions in every case, instead of the faster scalar instructions where it would have made sense to do so. For instance the iAPX 432 included a very expensive inter-module [[procedure call]] instruction, which the compiler used for all calls, despite the existence of much faster branch and link instructions. Another very slow call was enter_environment, which set up the memory protection. The compiler ran this for every single variable in the system, even when variables were used inside an existing environment and did not have to be checked. To make matters worse, data passed to and from procedures was always passed [[Evaluation strategy#Call by copy-restore|by value-return]] rather than by reference.  When running the [[Dhrystone]] benchmark, parameter passing took ten times longer than all other computations combined.<ref name="smotherman">Mark Smotherman, [http://people.cs.clemson.edu/~mark/432.html Overview of Intel 432]</ref>

According to the ''New York Times'', "the i432 ran 5 to 10 times more slowly than its competitor, the Motorola 68000".<ref name="MARKOFF">John Markoff, [https://www.nytimes.com/1998/04/05/business/inside-intel-the-future-is-riding-on-a-new-chip.html Inside Intel, The Future Is Riding on A New Chip], April 5, 1998</ref>

===Impact and similar designs===
The iAPX 432 was one of the first systems to implement the new [[IEEE-754]] Standard for Floating-Point Arithmetic.<ref>{{cite web|last1=Vickery|first1=Christopher|title=IEEE-754 Reference Material|url=http://babbage.cs.qc.cuny.edu/IEEE-754.old/References.xhtml|access-date=Dec 5, 2015|archive-date=December 1, 2011|archive-url=https://web.archive.org/web/20111201211023/http://babbage.cs.qc.cuny.edu/IEEE-754.old/References.xhtml|url-status=dead}}</ref>

An outcome of the failure of the 432 was that microprocessor designers concluded that object support in the chip leads to a complex design that will invariably run slowly, and the 432 was often cited as a counter-example by proponents of [[RISC]] designs. However, some hold that the OO support was not the primary problem with the 432, and that the implementation shortcomings (especially in the compiler) mentioned above would have made any CPU design slow. Since the iAPX 432 there has been only one other attempt at a similar design, the [[Rekursiv]] processor, although the [[INMOS Transputer]]'s process support was similar — and very fast.{{Citation needed|date=March 2016}} 

Intel had spent considerable time, money, and [[mindshare]] on the 432, had a skilled team devoted to it, and was unwilling to abandon it entirely after its failure in the marketplace. A new architect—[[Glenford Myers]]—was brought in to produce an entirely new architecture and implementation for the core processor, which would be built in a joint [[Intel]]/[[Siemens]] project (later [[BiiN]]), resulting in the [[Intel i960|i960]]-series processors. The i960 RISC subset became popular for a time in the embedded processor market, but the high-end 960MC and the tagged-memory 960MX were marketed only for military applications.

According to the ''New York Times'', Intel's collaboration with HP on the [[Itanium|Merced processor (later known as Itanium)]] was the company's comeback attempt for the very high-end market.<ref name="MARKOFF"/>