Editing Interrupt latency (section)

==Considerations==
Advanced interrupt controllers implement a multitude of hardware features in order to minimize the overhead during [[context switch]]es and the effective interrupt latency. These include features like:

* Minimum jitter through non-interruptible instructions<ref name="Yiu_2016_Latency"/>
* Zero wait states for the memory system<ref name="Yiu_2016_Latency"/>
* Switchable register banks<ref name="Yiu_2016_Latency"/>
* Tail chaining<ref name="Yiu_2016_Latency"/>
* Lazy stacking<ref name="Yiu_2016_Latency"/>
* Late arrival<ref name="Yiu_2016_Latency"/>
* Pop preemption<ref name="Yiu_2016_Latency"/>
* Sleep-on-exit feature<ref name="Yiu_2016_Latency"/>

Also, there are many other methods hardware may use to help lower the requirements for shorter interrupt latency in order to make a given interrupt latency tolerable in a situation. These include buffers, and [[flow control (data)|flow control]]. For example, most network cards implement transmit and receive [[ring buffer]]s, interrupt rate limiting, and hardware flow control. Buffers allow data to be stored until it can be transferred, and flow control allows the network card to pause communications without having to discard data if the buffer is full.

Modern hardware also implements interrupt rate limiting. This helps prevent [[interrupt storm]]s or [[live-lock]]s by having the hardware wait a programmable minimum amount of time between each interrupt it generates. Interrupt rate limiting reduces the amount of time spent servicing interrupts, allowing the processor to spend more time doing useful work. Exceeding this time results in a soft (recoverable) or hard (non-recoverable) error.