Editing Itanium (section)

=== Development: 1989–2001 ===
==== Inception: 1989–1994 ====
In 1989, HP started to research an architecture that would exceed the expected limits of the [[reduced instruction set computer]] (RISC) architectures caused by the great increase in complexity needed for executing multiple [[instructions per cycle]] due to the need for dynamic [[Data dependency|dependency]] checking and precise [[exception handling]].{{Efn|The size of the needed dependency-checking circuitry increases [[Quadratic growth|quadratically]] with the issue width.<ref name="simplicity"/><ref name="Understanding_EPIC"/>}} HP hired [[Bob Rau]] of [[Cydrome]] and [[Josh Fisher]] of [[Multiflow]], the pioneers of [[very long instruction word]] (VLIW) computing. One VLIW instruction word can contain several independent [[instruction (computer science)|instructions]], which can be executed in parallel without having to evaluate them for independence. A [[compiler]] must attempt to find [[Instruction-level parallelism|valid combinations of instructions that can be executed at the same time]], effectively performing the instruction scheduling that conventional [[superscalar processor]]s must do in hardware at runtime.

HP researchers modified the classic VLIW into a new type of architecture, later named [[Explicitly Parallel Instruction Computing]] (EPIC), which differs by: having template bits which show which instructions are independent inside and between the bundles of three instructions, which enables the explicitly parallel execution of multiple bundles and increasing the processors' [[Wide-issue|issue width]] without the need to recompile; by [[Predication (computer architecture)|predication]] of instructions to reduce the need for [[Branch (computer science)|branches]]; and by full interlocking to eliminate the [[delay slot]]s. In EPIC the assignment of [[execution unit]]s to instructions and the timing of their issuing can be decided by hardware, unlike in the classic VLIW. HP intended to use these features in PA-WideWord, the planned successor to their [[PA-RISC]] ISA. EPIC was intended to provide the best balance between the efficient use of silicon area and electricity, and general-purpose flexibility.<ref name="Understanding_EPIC">{{cite web |last1=Smotherman |first1=Mark |title=Understanding EPIC Architectures and Implementations |url=https://people.computing.clemson.edu/~mark/464/acmse_epic.pdf |publisher=[[Clemson University]] |access-date=5 June 2022}}</ref><ref name="HP_Labs">{{cite web
 | url=https://www.hpl.hp.com/news/2001/apr-jun/itanium.html
 | title=Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture
 | access-date=March 23, 2007
 | date=June 2001
 | work=[[HP Labs]]
 }}</ref> In 1993 HP held an internal competition to design the best (simulated) microarchitectures of a RISC and an EPIC type, led by Jerry Huck and [[Rajiv Gupta (technocrat)|Rajiv Gupta]] respectively. The EPIC team won, with over double the simulated performance of the RISC competitor.<ref name="nyt_merced">{{cite web |last1=Markoff |first1=John |title=Inside Intel, The Future is Riding on the Merced Chip |url=https://archive.org/details/TheJerusalemPost1998IsraelEnglish/Apr%2006%201998%2C%20The%20Jerusalem%20Post%2C%20%2319898%2C%20Israel%20%28en%29/page/n12/mode/1up |publisher=[[The New York Times]], republised by [[The Jerusalem Post]] |date=5 April 1998}}</ref>

At the same time Intel was also looking for ways to make better ISAs. In 1989 Intel had launched the [[Intel i860|i860]], which it marketed for workstations, servers, and [[Intel iPSC#iPSC/860|iPSC]] and [[Intel Paragon|Paragon]] supercomputers. It differed from other RISCs by being able to switch between the normal single instruction per cycle mode, and a mode where pairs of instructions are explicitly defined as parallel so as to execute them in the same cycle without having to do dependency checking. Another distinguishing feature were the instructions for an exposed floating-point pipeline, that enabled the tripling of throughput compared to the conventional floating-point instructions. Both of these features were left largely unused because compilers didn't support them, a problem that later challenged Itanium too. Without them, i860's parallelism (and thus performance) was no better than other RISCs, so it failed in the market. Itanium would adopt a more flexible form of explicit parallelism than i860 had.<ref>{{cite web |last1=DeMone |first1=Paul |title=Intel's History Lesson |url=https://www.realworldtech.com/intel-history-lesson/ |website=Real World Tech |date=25 January 2000}}</ref>

In November 1993 HP approached Intel, seeking collaboration on an innovative future architecture.<ref name="countdown">{{cite web |last1=DeMone |first1=Paul |title=Countdown to IA-64 |url=https://www.realworldtech.com/countdown-to-ia64/ |website=Real World Tech |date=14 March 2001}}</ref>{{refn|{{cite web |last1=Alpert |first1=Donald |title=Intel Itanium Processor (Merced) |url=https://camelback-comparch.com/about/technical-highlights/#merced |date=July 2003}} Alpert was the chief architect of the original P7 and the top engineering manager of Merced<ref>{{cite web |last1=Smotherman |first1=Mark |title=Who are the Computer Architects? |url=https://people.computing.clemson.edu/~mark/architects.html |publisher=[[Clemson University]] }} See the sections "Independence architecture" and "Wintel".</ref>}} At the time Intel was looking to extend x86 to 64 bits in a processor codenamed P7, which they found challenging.<ref>{{cite web |last1=DeMone |first1=Paul |title=What's Up With Willamette? (Part 1) |url=https://www.realworldtech.com/willamette-basics/ |website=Real World Tech |date=3 March 2000}}</ref> Later Intel claimed that four different design teams had explored 64-bit extensions, but each of them concluded that it was not economically feasible.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel takes slow road to 64-bit PC chips |url=https://www.cnet.com/tech/tech-industry/intel-takes-slow-road-to-64-bit-pc-chips/ |website=[[CNET]] |date=21 February 2003}}</ref> At the meeting with HP, Intel's engineers were impressed when Jerry Huck and [[Rajiv Gupta (technocrat)|Rajiv Gupta]] presented the PA-WideWord architecture they had designed to replace [[PA-RISC]]. "When we saw WideWord, we saw a lot of things we had only been looking at doing, already in their full glory", said Intel's [[John Crawford (engineer)|John Crawford]], who in 1994 became the chief architect of Merced, and who had earlier argued against extending the x86 with P7. HP's Gupta recalled: "I looked Albert Yu [Intel's general manager for microprocessors] in the eyes and showed him we could run circles around [[PowerPC]], that we could kill PowerPC, that we could kill the x86."<ref name="gambles"/> Soon Intel and HP started conducting in-depth technical discussions at an HP office, where each side had six{{Refn|<ref name="countdown"/><ref name="birth">{{cite web |last1=Britt |first1=Russ |title=The birth of a new processor |url=https://www.edn.com/the-birth-of-a-new-processor/ |website=[[EDN (magazine)|EDN]] |date=1 January 2000}}</ref> (The {{Define|ACM|architecture, compilers, microarchitecture}} committee with 5 people from each side<ref>{{cite web |last1=Smotherman |first1=Mark |title=Historical background for EPIC instruction set architectures |url=https://people.computing.clemson.edu/~mark/epic.html |publisher=[[Clemson University]] |access-date=3 June 2022}}</ref> was probably a different entity.)}} engineers who exchanged and discussed both companies' confidential architectural research. They then decided to use not only PA-WideWord, but also the more experimental [[HP Labs]] PlayDoh as the source of their joint future architecture.<ref name="simplicity">{{cite web |last1=DeMone |first1=Paul |title=HP's Struggle For Simplicity Ends at Intel |url=https://www.realworldtech.com/hp-intel-itanium/ |website=Real World Tech |date=27 October 1999}}</ref><ref>{{cite web |last1=Kathail |first1=Vinod |last2=Schlansker |first2=Michael S. |last3=Rau |first3=B. Ramakrishna |title=HPL-PD Architecture Specification: Version 1.1 |url=https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf |publisher=[[HP Labs|HP Laboratories]] |access-date=2023-07-05 |archive-date=2024-02-04 |archive-url=https://web.archive.org/web/20240204063521/https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf |url-status=dead }}</ref> Convinced of the superiority of the new project, in 1994 Intel canceled their existing plans for P7.

In June 1994 Intel and HP announced their joint effort to make a new ISA that would adopt ideas of Wide Word and VLIW. Yu declared: "If I were competitors, I'd be really worried. If you think you have a future, you don't."<ref name="gambles">{{cite web |last1=Hamilton |first1=David |title=Intel gambles with Itanium |url=https://www.zdnet.com/article/intel-gambles-with-itanium/ |website=[[ZDNet]] |date=28 May 2001}}</ref> On P7's future, Intel said the alliance would impact it, but "it is not clear" whether it would "fully encompass the new architecture".<ref>{{cite web |last1=Hecht |first1=Jeff |title=Technology: Intel opts for simpler, speedier chips |url=https://www.newscientist.com/article/mg14219303-300-technology-intel-opts-for-simpler-speedier-chips/ |website=[[New Scientist]] |date=18 June 1994}}</ref><ref>{{cite web |last1=Bozman |first1=Jean S. |title=Chip alliance shakes ground |url=https://books.google.com/books?id=QZtKFFB8weQC&pg=PA12 |website=[[Computerworld]] |date=13 June 1994}} David House had approved the project, but later severely criticized it.</ref>
Later the same month, Intel said that some of the first features of the new architecture would start appearing on Intel chips as early as the P7, but the full version would appear sometime later.<ref>{{cite web |last1=Babcock |first1=Charles |title=Silicon marriage: HP/Intel venture |url=https://books.google.com/books?id=QtpyKsPTNwkC&pg=PA6 |website=[[Computerworld]] |date=25 July 1994}}</ref>
In August 1994 [[EE Times]] reported that Intel told investors that P7 was being re-evaluated and possibly canceled in favor of the HP processor. Intel immediately issued a clarification, saying that P7 is still being defined, and that HP may contribute to its architecture. Later it was confirmed that the P7 codename had indeed passed to the HP-Intel processor. By early 1996 Intel revealed its new codename, ''Merced''.<ref>{{cite web |last1=DeMone |first1=Paul |title=Countdown to IA-64 |url=https://www.realworldtech.com/countdown-to-ia64/ |website=Real World Tech |date=14 March 2001}} Has a typo (P'''5''') in the graphic.</ref><ref>{{cite web |last1=Crothers |first1=Brooke |title=Intel aims to bring multimedia to the masses |url=https://books.google.com/books?id=zD4EAAAAMBAJ&pg=PA8 |website=[[InfoWorld]] |date=29 January 1996}}</ref>

HP believed that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so it partnered with Intel in 1994 to develop the IA-64 architecture, derived from EPIC. Intel was willing to undertake the very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in 1998.<ref name="HP_Labs"/>

==== Design and delays: 1994–2001 ====
Merced was designed by a team of 500, which Intel later admitted was too inexperienced, with many recent college graduates. Crawford (Intel) was the chief architect, while Huck (HP) held the second position. Early in the development HP and Intel had a disagreement where Intel wanted more dedicated hardware for more floating-point instructions. HP prevailed upon the discovery of [[Pentium FDIV bug|a floating-point hardware bug]] in Intel's [[Pentium (original)|Pentium]]. When Merced was [[Floorplan (microelectronics)|floorplanned]] for the first time in mid-1996, it turned out to be far too large, "this was a lot worse than anything I'd seen before", said Crawford. The designers had to reduce the complexity (and thus performance) of subsystems, including the x86 unit and cutting the L2 cache to 96 KB.{{Efn|For comparison the 180nm Pentium III Xeon MP had a 2 MB on-die L2 cache.}} Eventually it was agreed that the size target could only be reached by using the [[180 nm]] process instead of the intended [[250 nm process|250 nm]]. Later problems emerged with attempts to speed up the critical paths without disturbing the other circuits' speed. Merced was [[Tape-out|taped out]] on 4 July 1999, and in August Intel produced the first complete test chip.<ref name="gambles"/>

The expectations for Merced waned over time as delays and performance deficiencies emerged, shifting the focus and onus for success onto the HP-led second Itanium design, codenamed ''McKinley''. In July 1997 the switch to the [[180 nm process]] delayed Merced into the second half of 1999.<ref>{{cite web |title=Merced "Will Be Out Late 1999," Says Hewlett-Packard |url=https://techmonitor.ai/technology/merced_will_be_out_late_1999_says_hewlett_packard_1 |agency=Computer Business Review |website=Tech Monitor |date=18 July 1997 |url-status=live |archive-url=https://archive.today/20240213040233/https://techmonitor.ai/technology/merced_will_be_out_late_1999_says_hewlett_packard_1 |archive-date= 13 February 2024 }}</ref> Shortly before the reveal of [[Explicitly parallel instruction computing|EPIC]] at the Microprocessor Forum in October 1997, an analyst of the [[Microprocessor Report]] said that Itanium would "not show the competitive performance until 2001. It will take the second version of the chip for the performance to get shown".<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel late to 64-bit computing |url=https://www.cnet.com/news/intel-late-to-64-bit-computing/ |website=[[CNET]] |date=6 October 1997 |url-status=live |archive-url=https://web.archive.org/web/20220627172827/https://www.cnet.com/tech/tech-industry/intel-late-to-64-bit-computing/ |archive-date= Jun 27, 2022 }}</ref> At the Forum, Intel's [[Fred Pollack]] originated the "wait for McKinley" mantra when he said that it would double the Merced's performance and would "knock your socks off",<ref name="cnet_unveil_epic">{{cite web |last1=Kanellos |first1=Michael |title=Intel, HP unveil EPIC technology |url=https://www.cnet.com/news/intel-hp-unveil-epic-technology/ |website=[[CNET]] |date=14 October 1997 |url-status=live |archive-url=https://web.archive.org/web/20220818183735/https://www.cnet.com/tech/tech-industry/intel-hp-unveil-epic-technology/ |archive-date= Aug 18, 2022 }}</ref><ref>{{cite web |last1=DeMone |first1=Paul |title=HP's Struggle For Simplicity Ends at Intel |url=https://www.realworldtech.com/hp-intel-itanium/3/ |website=Real World Tech |page=3 |date=27 October 1999 |url-status=live |archive-url=https://web.archive.org/web/20231031163355/https://www.realworldtech.com/hp-intel-itanium/3/ |archive-date= Oct 31, 2023 }}</ref> while using the same 180 nm process as Merced.<ref>{{cite news |last1=Gwennap |first1=Linley |title=Intel, HP Make EPIC Disclosure |url=https://www.cs.virginia.edu/~skadron/cs854_uproc_survey/spring_2001/cs854/111401.pdf |work=[[Microprocessor Report]] |volume=11 |issue=14 |date=27 October 1997 |url-status=live |archive-url= https://web.archive.org/web/20231031163335/https://www.cs.virginia.edu/~skadron/cs854_uproc_survey/spring_2001/cs854/111401.pdf |archive-date= Oct 31, 2023 }}</ref> Pollack also said that Merced's x86 performance would be lower than the fastest x86 processors, and that x86 would "continue to grow at its historical rates".<ref name="cnet_unveil_epic"/> Intel said that IA-64 won't have much presence in the consumer market for 5 to 10 years.<ref>{{cite news |last1=Corcoran |first1=Elizabeth |title=Chipmakers unveil works in progress |url=https://www.washingtonpost.com/archive/business/1997/10/15/chipmakers-unveil-works-in-progress/b4ecf2c5-7c6b-419e-a0d1-9c35d515b5e0/ |url-access=subscription |newspaper=[[The Washington Post]] |date=15 October 1997 |url-status=live |archive-url= https://archive.today/20240213044222/https://www.washingtonpost.com/archive/business/1997/10/15/chipmakers-unveil-works-in-progress/b4ecf2c5-7c6b-419e-a0d1-9c35d515b5e0/|archive-date= 13 February 2024 }}</ref>

Later it was reported that HP's motivation when starting to design McKinley in 1996 was to have more control over the project so as to avoid the issues affecting Merced's performance and schedule.<ref name="zdnet_wait">{{cite web |last1=Robertson |first1=Chiyo |title=Merced: Worth the wait? What of McKinley? |url=https://www.zdnet.com/article/merced-worth-the-wait-what-of-mckinley/ |website=[[ZDNet]] |date=17 March 1999}}</ref><ref>{{cite web |last1=Matsumoto |first1=Craig |title=Intel outlines road to McKinley processor |url=https://www.eetimes.com/intel-outlines-road-to-mckinley-processor/ |website=[[EE Times]] |date=8 October 1998}}</ref> The design team finalized McKinley's project goals in 1997.<ref name="HP_McKinley_wp">{{cite CiteSeerX |title=Inside the Intel Itanium 2 Processor: a Hewlett Packard Technical White Paper |date=17 July 2002 | citeseerx=10.1.1.96.8209 }}</ref> In late May 1998 Merced was delayed to mid-2000, and by August 1998 analysts were questioning its commercial viability, given that McKinley would arrive shortly after with double the performance, as delays were causing Merced to turn into simply a development vehicle for the Itanium ecosystem. The "wait for McKinley" narrative was becoming prevalent.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Is Merced doomed? |url=https://www.cnet.com/tech/tech-industry/is-merced-doomed/ |website=[[CNET]] |date=6 August 1998}}</ref> The same day it was reported that due to the delays, HP would extend its line of PA-RISC [[PA-8000]] series processors from PA-8500 to as far as PA-8900.<ref>{{cite news |title=INTEL'S MERCED COULD BE ECLIPSED BY MCKINLEY FOLLOW-ON |url=https://techmonitor.ai/technology/intels_merced_could_be_eclipsed_by_mckinley_follow_on |newspaper=Tech Monitor |date=6 August 1998}}</ref> In October 1998 HP announced its plans for four more generations of PA-RISC processors, with PA-8900 set to reach 1.2 GHz in 2003.<ref>{{cite web |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=HP has two-pronged chip plan |url=http://cnet.com/news/0-1004-200-334214.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20001203183700/http://cnet.com/news/0-1004-200-334214.html |archive-date=2000-12-03 |date=13 October 1998}}</ref>

By March 1999 some analysts expected Merced to ship in volume only in 2001, but the volume was widely expected to be low as most customers would wait for McKinley.<ref name="zdnet_wait"/> In May 1999, two months before Merced's [[tape-out]], an analyst said that failure to tape-out before July would result in another delay.<ref>{{cite web |last1=Gary |first1=Gregory |title=IA 64 Update: Part 1 of 2 |url=https://www.edn.com/ia-64-update-part-1-of-2/ |website=[[EDN (magazine)|EDN]] |date=3 May 1999}}</ref> In July 1999, upon reports that the first silicon would be made in late August, analysts predicted a delay to late 2000, and came into agreement that Merced would be used chiefly for debugging and testing the IA-64 software. Linley Gwennap of [[Microprocessor Report|MPR]] said of Merced that "at this point, everyone is expecting it's going to be late and slow, and the real advance is going to come from McKinley. What this does is puts a lot more pressure on McKinley and for that team to deliver".<ref name="may_slip">{{cite web |last1=Shankland |first1=Stephen |title=Intel's Merced chip may slip further |url=http://news.cnet.com/news/0-1003-200-344601.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20000605083119/http://news.cnet.com/news/0-1003-200-344601.html |archive-date=2000-06-05 |date=8 July 1999}}</ref> By then, Intel had revealed that Merced would be initially priced at $5000.<ref>{{cite web |last1=Hamblen |first1=Matt |title=Intel: No Forced March to Merced |url=https://books.google.com/books?id=51iIcvzoX-AC&pg=PA61 |website=[[Computerworld]] |date=12 July 1999}}</ref> In August 1999 HP advised some of their customers to skip Merced and wait for McKinley.<ref>{{cite web |last1=Shankland |first1=Stephen |title=HP upgrade path bypasses Merced chip |url=http://news.cnet.com/news/0-1003-200-346220.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20000819022147/http://news.cnet.com/news/0-1003-200-346220.html |archive-date=2000-08-19 |date=19 August 1999}}</ref> By July 2000 HP told the press that the first Itanium systems would be for niche uses, and that "You're not going to put this stuff near your data center for several years."; HP expected its Itanium systems to outsell the PA-RISC systems only in 2005.<ref>{{cite web |last1=Shankland |first1=Stephen |title=HP moves slowly into world of Intel 64-bit processors |url=http://www.news.cnet.com/news/0-1003-200-2241414.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20010210011931/http://www.news.cnet.com/news/0-1003-200-2241414.html |archive-date=2001-02-10 |date=11 July 2000}}</ref> The same July Intel told of another delay, due to a [[Stepping level|stepping]] change to fix bugs. Now only "pilot systems" would ship that year, while the general availability was pushed to the "first half of 2001". Server makers had largely forgone spending on the R&D for the Merced-based systems, instead using motherboards or whole servers of Intel's design. To foster a wide ecosystem, by mid-2000 Intel had provided 15,000 Itaniums in 5,000 systems to software developers and hardware designers.<ref>{{cite web |last1=Shankland |first1=Stephen |last2=Kanellos |first2=Michael |title=Intel pushes back schedule for Itanium chip |url=http://news.cnet.com/news/0-1003-200-2284759.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20010413122744/http://news.cnet.com/news/0-1003-200-2284759.html |archive-date=2001-04-13 |date=July 18, 2000}}</ref> In March 2001 Intel said Itanium systems would begin shipping to customers in the second quarter, followed by a broader deployment in the second half of the year. By then even Intel publicly acknowledged that many customers would wait for McKinley.<ref>{{cite web |last1=Shankland |first1=Stephen |title=Intel draws out Itanium arrival |url=http://news.cnet.com/news/0-1003-200-4996738.html |website=[[CNET]] |archive-url=https://web.archive.org/web/20010413151817/http://news.cnet.com/news/0-1003-200-4996738.html |archive-date=2001-04-13 |date=1 March 2001}}</ref>
[[Image:Itanium Sales Forecasts edit.png|thumb|right|400px|Itanium Server Sales forecast history<ref name="IDC_chart">{{cite web
 | url=http://www.zdnet.com/pictures/charts-mining-itanium/
 | title=Mining Itanium
 | access-date=March 19, 2007
 | date=December 7, 2005
 | work=CNet News
 | archive-date=June 11, 2018
 | archive-url=https://web.archive.org/web/20180611040452/https://www.zdnet.com/pictures/charts-mining-itanium/
 | url-status=dead
 }}</ref><ref name="IDC 2006">{{cite news
 | url=https://www.cnet.com/news/analyst-firm-offers-rosy-view-of-itanium/
 | title=Analyst firm offers rosy view of Itanium
 | access-date=March 20, 2007
 | last=Shankland
 | first=Stephen
 | date=February 14, 2006
 | publisher=[[CNET|CNET News]]
 | archive-date=June 24, 2016
 | archive-url=https://web.archive.org/web/20160624090721/http://www.cnet.com/news/analyst-firm-offers-rosy-view-of-itanium/
 | url-status=live
 }}</ref>]]

==== Expectations ====
During development, Intel, HP, and industry analysts predicted that IA-64 would dominate first in 64-bit servers and workstations, then expand to the lower-end servers, supplanting Xeon, and finally penetrate into the [[personal computer]]s, eventually to supplant RISC and [[complex instruction set computing]] (CISC) architectures for all general-purpose applications, though not replacing x86 "for the foreseeable future" according to Intel.<ref>{{cite web |last1=Halfhill |first1=Tom R. |title=Beyond Pentium II |url=http://www.byte.com/art/9712/sec5/art1.htm |website=[[Byte (magazine)|Byte]] |archive-url=https://web.archive.org/web/20000302143120/http://www.byte.com/art/9712/sec5/art1.htm |archive-date=2000-03-02 |url-status=dead |date=December 1997}}</ref><ref name="nyt_merced"/><ref>{{cite web |last1=Connor |first1=Deni |title=Intel's Merced will coexist with 32-bit chips |url=https://books.google.com/books?id=AxwEAAAAMBAJ&pg=PA61 |website=[[Network World]] |date=1 March 1999}}</ref><ref>{{cite web |last1=Knorr |first1=Eric |title=Upgrading your server: A look at the Itanium |url=https://www.zdnet.com/article/upgrading-your-server-a-look-at-the-itanium/ |website=[[ZDNet]] |date=10 September 2001}}</ref><ref name="anand">{{cite web
 | url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2598
 | title=Itanium–Is there light at the end of the tunnel?
 | access-date=March 23, 2007
 | last=De Gelas
 | first=Johan
 | date=November 9, 2005
 | work=[[AnandTech]]
 | archive-date=May 3, 2012
 | archive-url=https://web.archive.org/web/20120503094946/http://www.anandtech.com/show/1854
 | url-status=live
 }}</ref><ref name="Venturebeat">{{cite web
 | url=https://venturebeat.com/2009/05/08/exit-interview-retiring-intel-chairman-craig-barrett-on-the-industrys-unfinished-business/
 | title=Exit interview: Retiring Intel chairman Craig Barrett on the industry's unfinished business
 | access-date=May 17, 2009
 | last=Takahashi
 | first=Dean
 | date=May 8, 2009
 | work=VentureBeat
 | archive-date=April 21, 2018
 | archive-url=https://web.archive.org/web/20180421095016/https://venturebeat.com/2009/05/08/exit-interview-retiring-intel-chairman-craig-barrett-on-the-industrys-unfinished-business/
 | url-status=live
 }}</ref> In 1997-1998, Intel CEO [[Andy Grove]] predicted that Itanium would not come to the desktop computers for four of five years after launch, and said "I don't see Merced appearing on a mainstream desktop inside of a decade".<ref>{{cite web |last1=Nash |first1=Kim S. |title=Behind the Merced Mystique |url=https://books.google.com/books?id=03nTlQZ61IgC&pg=PT14 |website=[[Computerworld]] |date=6 July 1998}}</ref><ref name="nyt_merced"/> In contrast, Itanium was expected to capture 70% of the 64-bit server market in 2002.<ref>{{cite web |last1=Yu |first1=Elleen |title=IA-64 to overtake RISC |url=https://www.arnnet.com.au/article/110877/ia-64_overtake_risc/ |website=ARN |date=25 November 1998 |access-date=16 August 2022 |archive-date=29 January 2023 |archive-url=https://web.archive.org/web/20230129171855/https://www.arnnet.com.au/article/110877/ia-64_overtake_risc/ |url-status=dead }}</ref> Already in 1998 Itanium's focus on the high end of the computer market was criticized for making it vulnerable to challengers expanding from the lower-end market segments, but many people in the computer industry feared voicing doubts about Itanium in the fear of Intel's retaliation.<ref name="nyt_merced"/>
[[Compaq]] and [[Silicon Graphics]] decided to abandon further development of the [[DEC Alpha|Alpha]] and [[MIPS architecture|MIPS]] architectures respectively in favor of migrating to IA-64.<ref name="cautionary">{{cite web
 | url=https://www.zdnet.com/article/itanium-a-cautionary-tale/
 | title=Itanium: A cautionary tale
 | access-date=January 1, 2019
 | date=December 7, 2005
 | work=Tech News on ZDNet
 | archive-date=August 2, 2020
 | archive-url=https://web.archive.org/web/20200802000433/https://www.zdnet.com/article/itanium-a-cautionary-tale/
 | url-status=live
 }}</ref>

Several groups ported operating systems for the architecture, including [[Microsoft Windows]], [[OpenVMS]], [[Linux]], [[HP-UX]], [[Solaris (operating system)|Solaris]],<ref name="Solaris-Merced1">{{cite web
 | url=http://www.computerworld.com/home/news.nsf/all/9909013sunsol
 | title=Solaris for IA-64 coming this fall
 | last=Vijayan
 | first=Jaikumar
 | date=September 1, 1999
 | website=[[Computerworld]]
 | archive-date=January 15, 2000
 | archive-url=https://web.archive.org/web/20000115084746/http://www.computerworld.com/home/news.nsf/all/9909013sunsol
 | url-status=dead
 }}</ref><ref name="Solaris-Merced2">{{cite news |url=https://www.eetimes.com/core-logic-efforts-under-way-for-merced/ |title=Core-logic efforts under way for Merced |last=Wolfe |first=Alexander |access-date=December 17, 2019 |date=September 2, 1999 |magazine=[[EE Times]] |archive-date=December 17, 2019 |archive-url=https://web.archive.org/web/20191217201650/https://www.eetimes.com/core-logic-efforts-under-way-for-merced/ |url-status=live }}</ref><ref name="Solaris-Merced3">{{cite web
 | url=http://www.thefreelibrary.com/Sun+Introduces+Solaris+Developer+Kit+for+Intel+to+Speed+Development...-a020369933
 | title=Sun Introduces Solaris Developer Kit for Intel to Speed Development of Applications On Solaris; Award-winning Sun Tools Help ISVs Easily Develop for Solaris on Intel Today
 | access-date=June 6, 2016
 | date=March 10, 1998
 | work=Business Wire
 | quote=...developers can quickly develop applications today that will be compatible with and can easily be tuned for Solaris on Merced.
 | archive-date=August 5, 2016
 | archive-url=https://web.archive.org/web/20160805145446/http://www.thefreelibrary.com/Sun+Introduces+Solaris+Developer+Kit+for+Intel+to+Speed+Development...-a020369933
 | url-status=dead
 }}</ref>
[[Tru64 UNIX]],<ref name="cautionary"/> and [[Project Monterey|Monterey/64]].<ref>{{cite news
 | url=https://www.cnet.com/tech/tech-industry/next-generation-chip-passes-key-milestone/
 | title=Next-generation chip passes key milestone
 | last=Shankland
 | first=Stephen
 | date=September 17, 1999
 | publisher=[[CNET|CNET News]]
 }}</ref>
The latter three were canceled before reaching the market. By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery timeframe of Merced began slipping.<ref name="may_slip"/>

Intel announced the official name of the processor, ''Itanium'', on October 4, 1999.<ref>{{cite web
 | url=https://www.cnet.com/tech/tech-industry/intel-names-merced-chip-itanium/
 | title=Intel names Merced chip Itanium
 | access-date=April 30, 2007
 | last=Kanellos
 | first=Michael
 | date=October 4, 1999
 | website=[[CNET]]
 }}</ref>
Within hours, the name '''''Itanic''''' had been coined on a [[Usenet]] newsgroup, a reference to the [[RMS Titanic|RMS ''Titanic'']], the "unsinkable" [[ocean liner]] that sank on her maiden voyage in 1912.<ref>{{cite newsgroup
 | url=https://groups.google.com/d/msg/comp.sys.mac.advocacy/UiOOaXF3-lI/f3nje9CHPx0J
 | title=Re:Itanium
 | access-date=May 20, 2020
 | last=Finstad
 | first=Kraig
 | date=October 4, 1999
 | newsgroup=comp.sys.mac.advocacy
 }}</ref> "Itanic" was then used often by ''[[The Register]]'',<ref name="Reg_Itanic">{{cite news
 | first=Pete
 | last=Sherriff
 | title=AMD vs Intel&nbsp;– our readers write
 | url=https://www.theregister.com/1999/10/28/amd_vs_intel_our_readers/
 | work=[[The Register]]
 | date=October 28, 1999
 | access-date=November 25, 2022
 }}</ref> and others,<ref>{{cite web
 |url          = https://www.zdnet.com/article/interpreting-mcnealys-lexicon/
 |title        = Interpreting McNealy's lexicon
 |access-date  = March 19, 2007
 |last         = Berlind
 |first        = David
 |date         = November 30, 2001
 |work         = [[ZDNet]] Tech Update
 |archive-date = September 4, 2019
 |archive-url  = https://web.archive.org/web/20190904215102/https://www.zdnet.com/article/interpreting-mcnealys-lexicon/
 |url-status   = live
}}</ref><ref>{{cite web
|url=http://www.theinquirer.net/inquirer/news/1004260/itanic-shell-game-continues
|url-status=unfit
|archive-url=https://web.archive.org/web/20160305085136/http://www.theinquirer.net/inquirer/news/1004260/itanic-shell-game-continues
|archive-date=March 5, 2016
|title=Itanic shell game continues
|access-date=February 27, 2016
|last=Demerjian
|first=Charlie
|date=July 18, 2006
|website=[[The Inquirer]]
}}</ref><ref>{{cite news|url=https://www.nytimes.com/2003/10/19/business/market-watch-fawning-analysts-betray-investors.html|title=Fawning Analysts Betray Investors|last=Morgenson|first=Gretchen|date=October 19, 2003|work=[[The New York Times]]|access-date=January 1, 2019|archive-date=October 11, 2012|archive-url=https://web.archive.org/web/20121011211448/http://www.zdnet.com/news/interpreting-mcnealys-lexicon/296322|url-status=live}}</ref> to imply that the multibillion-dollar investment in Itanium—and the early hype associated with it—would be followed by its relatively quick demise.