Editing Logic gate (section)

== Symbols <!--This section is linked from [[Schematic]]: do not rename heading without including an anchor to previous name ([[MOS:HEAD]])--> ==
[[File:74LS192 Symbol.png|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 60617-12.|class=skin-invert-image]]
There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany.

The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor.

IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another.

In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]].

{| class="wikitable" style="text-align:center;"
|-
! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]]
|-
! colspan="5" | Single-input gates
|-
| '''[[Buffer gate|Buffer]]'''
|
[[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]]
|
[[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]]
| <math>{A}</math>
|
{| class="wikitable" style="float:right;text-align:center;"
|-  style="background:#def;"
|'''Input''' || '''Output'''
|- style="background:#def;"
| A || Q
|-
| {{no2|0}} || {{no2|0}}
|-
| {{yes2|1}} || {{yes2|1}}
|}
|-
| '''[[NOT gate|NOT]]'''<br />(inverter)
|
[[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]]
|
[[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]]
| <math>\overline{A}</math> or <math>\neg A</math>
|
{| class="wikitable" style="float:right;"
|-  style="background:#def; text-align:center;"
| '''Input''' || '''Output'''
|- style="background:#def; text-align:center;"
| A || Q
|-
| {{no2|0}} || {{yes2|1}}
|-
| {{yes2|1}} || {{no2|0}}
|}
|-
| colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful.
|-
! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]]
|-
| '''[[AND gate|AND]]'''
|
[[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]]
|
[[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]]
| <math>A \cdot B</math> or <math>A \land B</math>
|
{| class="wikitable" style="float:right;text-align:center;"
|-  style="background:#def;"
|colspan=2|'''Input''' || '''Output'''
|-  style="background:#def;"
| A || B || Q
|-
| {{no2|0}} || {{no2|0}} || {{no2|0}}
|-
| {{no2|0}} || {{yes2|1}} || {{no2|0}}
|-
| {{yes2|1}} || {{no2|0}} || {{no2|0}}
|-"
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}}
|}
|-
| '''[[OR gate|OR]]'''
|
[[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]]
|
[[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]]
| <math>A+B</math> or <math>A \lor B</math>
|
{| class="wikitable" style="float:right;text-align:center;"
|-  style="background:#def;"
|colspan=2|'''Input''' || '''Output'''
|-  style="background:#def"
| A || B || Q
|- 
| {{no2|0}} || {{no2|0}} || {{no2|0}}
|-
| {{no2|0}} || {{yes2|1}} || {{yes2|1}}
|-
| {{yes2|1}} || {{no2|0}} || {{yes2|1}}
|-
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}}
|}
|-
! colspan="5" |[[Alternative denial]] and [[joint denial]]
|-
| '''[[NAND gate|NAND]]'''
|
[[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]]
|
[[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]]
| <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math>
|
{| class="wikitable" style="float:right;text-align:center;"
|-  style="background:#def;"
|colspan=2|'''Input''' || '''Output'''
|-  style="background:#def;"
| A || B || Q
|-
| {{no2|0}} || {{no2|0}} || {{yes2|1}}
|-
| {{no2|0}} || {{yes2|1}} || {{yes2|1}}
|-
| {{yes2|1}} || {{no2|0}} || {{yes2|1}}
|-
| {{yes2|1}} || {{yes2|1}} || {{no2|0}}
|}
|-
| '''[[NOR gate|NOR]]'''
| [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]]
| [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]]
| <math>\overline{A + B}</math> or <math>A \downarrow B</math>
|
{| class="wikitable" style="float:right;text-align:center;"
|-  style="background:#def;"
|colspan=2|'''Input''' || '''Output'''
|-  style="background:#def;"
| A || B || Q
|- 
| {{no2|0}} || {{no2|0}} || {{yes2|1}}
|- 
| {{no2|0}} || {{yes2|1}} || {{no2|0}}
|- 
| {{yes2|1}} || {{no2|0}} || {{no2|0}}
|-
| {{yes2|1}} || {{yes2|1}} || {{no2|0}}
|}
|-
! colspan="5" |[[Exclusive or]] and [[biconditional]]
|-
| '''[[XOR gate|XOR]]'''
| [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]]
| [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]]
| <math>A \oplus B</math> or <math>A \veebar B</math>
|
{| class="wikitable" style="float:right;text-align:center;"
|-  style="background:#def;"
|colspan=2|'''Input''' || '''Output'''
|-  style="background:#def;"
| A || B || Q
|-
| {{no2|0}} || {{no2|0}} || {{no2|0}}
|-
| {{no2|0}} || {{yes2|1}} || {{yes2|1}}
|-
| {{yes2|1}} || {{no2|0}} || {{yes2|1}}
|-
| {{yes2|1}} || {{yes2|1}} || {{no2|0}}
|}
|-
| colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol.
|-
| '''[[XNOR]]'''
| [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]]
| [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]]
| <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math>
|
{| class="wikitable" style="float:right;text-align:center;"
|-  style="background:#def;"
|colspan=2|'''Input''' || '''Output'''
|-  style="background:#def;"
| A || B || Q
|-
| {{no2|0}} || {{no2|0}} || {{yes2|1}}
|-
| {{no2|0}} || {{yes2|1}} || {{no2|0}}
|-
| {{yes2|1}} || {{no2|0}} || {{no2|0}}
|-
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}}
|}
|-
! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]]
|-
| '''[[IMPLY]]'''<ref>{{cite book|title=VLSI, Microwave and Wireless Technologies|editor1=Brijesh Mishra|editor2=Manish Tiwari|chapter=Memristor Emulator Circuits an Emerging Technology with Applications|author1=Jyoti Garg|author2=Aishita Verma|author3=Subodh Wairya|page=476}}</ref><ref>{{cite book|title=Cellular Computing|last=Hanawalt|first=Barbara|page=52|url=https://www.google.com/books/edition/Cellular_Computing/iEQj_WFuwFIC?hl=en&gbpv=1&pg=PA52}}</ref>
| 
| 
| <math>\overline{A}+B</math> or <math>A \rightarrow B</math>
|
{| class="wikitable" style="float:right;text-align:center;"
|-  style="background:#def;"
|colspan=2|'''Input''' || '''Output'''
|-  style="background:#def;"
| A || B || Q
|-
| {{no2|0}} || {{no2|0}} || {{yes2|1}}
|-
| {{no2|0}} || {{yes2|1}} || {{yes2|1}}
|-
| {{yes2|1}} || {{no2|0}} || {{no2|0}}
|-
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}}
|}
|-
| '''[[NIMPLY]]'''
| 
| 
| <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math>
|
{| class="wikitable" style="float:right;text-align:center;"
|-  style="background:#def;"
|colspan=2|'''Input''' || '''Output'''
|-  style="background:#def;"
| A || B || Q
|-
| {{no2|0}} || {{no2|0}} || {{no2|0}}
|-
| {{no2|0}} || {{yes2|1}} || {{no2|0}}
|-
| {{yes2|1}} || {{no2|0}} || {{yes2|1}}
|-
| {{yes2|1}} || {{yes2|1}} || {{no2|0}}
|}
|-
| colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false.
|}