Editing Logical effort (section)

==Procedure for calculating the logical effort of a single stage==
CMOS inverters along the critical path are typically designed with a gamma equal to 2.
In other words, the pFET of the inverter is designed with twice the width (and therefore twice the capacitance) as the nFET of the inverter,
in order to get roughly the same [[Power MOSFET#P-substrate power MOSFET|pFET resistance]] as nFET resistance, in order to get roughly equal pull-up current and pull-down current.<ref>{{cite web|first= Jason D.|last= Bakos|title= Fundamentals of VLSI Chip Design|page= 23|url= http://www.kgsepg.com/project-id/11076-fundamentals-vlsi-chip-design|accessdate= 8 March 2011|publisher= University of South Carolina|url-status= dead|archiveurl= https://web.archive.org/web/20111108220326/http://www.kgsepg.com/project-id/11076-fundamentals-vlsi-chip-design|archivedate= 8 November 2011}}
</ref><ref>
{{cite book|first1=M.|first2=J. F. M.|last1= Dielen| last2=Theeuwen| title=An Optimal CMOS Structure for the Design of a Cell Library| year=1987| page=11|bibcode=1987cmos.rept.....D }}
</ref>

Choose sizes for all transistors such that the output drive of the gate is equal to the output drive of an inverter built from a size-2 PMOS and a size-1 NMOS.

The output drive of a gate is equal to the minimum – over all possible combinations of inputs – of the output drive of the gate for that input.

The output drive of a gate for a given input is equal to the drive at its output node.

The drive at a node is equal to the sum of the drives of all transistors which are enabled and whose source or drain is in contact with the node in question.  A PMOS transistor is enabled when its gate voltage is 0.  An NMOS transistor is enabled when its gate voltage is 1.

Once sizes have been chosen, the logical effort of the output of the gate is the sum of the widths of all transistors whose source or drain is in contact with the output node.  The logical effort of each input to the gate is the sum of the widths of all transistors whose gate is in contact with that input node.

The logical effort of the entire gate is the ratio of its output logical effort to the sum of its input logical efforts.