Editing Magnetoresistive RAM (section)

== Comparison with other systems ==
===Density===
The main determinant of a memory system's cost is the density of the components used to make it up. Smaller components, and fewer of them, mean that more "cells" can be packed onto a single chip, which in turn means more can be produced at once from a single silicon wafer. This improves yield, which is directly related to cost.

DRAM uses a small [[capacitor]] as a memory element, wires to carry current to and from it, and a [[transistor]] to control it – referred to as a "1T1C" cell. This makes DRAM the highest-density RAM currently available, and thus the least expensive, which is why it is used for the majority of RAM found in computers.

MRAM is physically similar to DRAM in makeup, and often does require a transistor for the write operation (though not strictly necessary). The scaling of transistors to higher density necessarily leads to lower available current, which could limit MRAM performance at advanced nodes.

===Power consumption===
Since the capacitors used in DRAM lose their charge over time, memory assemblies that use DRAM must [[memory refresh|''refresh'']] all the cells in their chips several times a second, reading each one and re-writing its contents. As DRAM cells decrease in size it is necessary to refresh the cells more often, resulting in greater power consumption.

In contrast, MRAM never requires a refresh. This means that not only does it retain its memory with the power turned off but also there is no constant power-draw. While the read process in theory requires more power than the same process in a DRAM, in practice the difference appears to be very close to zero. However, the write process requires more power to overcome the existing field stored in the junction, varying from three to eight times the power required during reading.<ref>{{cite web |first1=W.J. |last1=Gallagher |first2=S.S.P. |last2=Parkin |url=http://www.research.ibm.com/journal/rd/501/gallagher.html |title=Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip |publisher=IBM |date=24 January 2006}}</ref><ref>{{cite web |first=Rajagopalan |last=Desikan |display-authors=etal |url=http://www.research.ibm.com/people/l/lefurgy/Publications/mram-tr2002-47.pdf |title=On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories |publisher=Department of Computer Sciences, University of Texas at Austin |date=27 September 2002}}</ref> Although the exact amount of power savings depends on the nature of the work&nbsp;— more frequent writing will require more power – in general MRAM proponents expect much [[low-power electronics|lower power consumption]] (up to 99% less) compared to DRAM. STT-based MRAMs eliminate the difference between reading and writing, further reducing power requirements.

It is also worth comparing MRAM with another common memory system&nbsp;— [[Flash memory|flash RAM]]. Like MRAM, flash does not lose its memory when power is removed, which makes it very common in applications requiring persistent storage. When used for reading, flash and MRAM are very similar in power requirements. However, flash is re-written using a large pulse of voltage (about 10 V) that is stored up over time in a [[charge pump]], which is both power-hungry and time-consuming. In addition, the current pulse physically degrades the flash cells, which means flash can only be written to some finite number of times before it must be replaced.

In contrast, MRAM requires only slightly more power to write than read, and no change in the voltage, eliminating the need for a charge pump. This leads to much faster operation, lower power consumption, and an indefinitely long lifetime.

===Data retention===
MRAM is often touted as being a non-volatile memory. However, the current mainstream high-capacity MRAM, spin-transfer torque memory, provides improved retention at the cost of higher power consumption, ''i.e.'', higher write current. In particular, the critical (minimum) write current is directly proportional to the thermal stability factor Δ.<ref>{{Cite web|url=https://www.cs.utah.edu/thememoryforum/jin.pdf|title=Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory}}</ref> The retention is in turn proportional to exp(Δ). The retention, therefore, degrades exponentially with reduced write current.

===Speed===
[[Dynamic random-access memory]] (DRAM) performance is limited by the rate at which the charge stored in the cells can be drained (for reading) or stored (for writing). MRAM operation is based on measuring voltages rather than charges or currents, so there is less "settling time" needed. IBM researchers have demonstrated MRAM devices with access times on the order of 2&nbsp;ns, somewhat better than even the most advanced DRAMs built on much newer processes.<ref>[http://www.thic.org/pdf/Jul03/nist.skaka.030722.pdf "Past, Present and Future of MRAM"], NIST Magnetic Technology, 22 July 2003</ref> A team at the German [[Physikalisch-Technische Bundesanstalt]] have demonstrated MRAM devices with 1&nbsp;ns settling times, better than the currently accepted theoretical limits for DRAM, although the demonstration was a single cell.<ref>Kate McAlpine, [https://www.newscientist.com/channel/tech/dn14525-spin-flip-trick-points-to-fastest-ram-yet.html "Spin flip trick points to fastest RAM yet"], ''NewScientist'', 13 August 2008</ref> The differences compared to flash are far more significant, with write speeds as much as thousands of times faster. However, these speed comparisons are not for like-for-like current. High-density memory requires small transistors with reduced current, especially when built for low standby leakage. Under such conditions, write times shorter than 30&nbsp;ns may not be reached so easily. In particular, to meet solder reflow stability of 260&nbsp;°C over 90 seconds, 250&nbsp;ns pulses have been required.<ref>L. Thomas et al., S3S 2017</ref> This is related to the elevated thermal stability requirement driving up the write bit error rate. In order to avoid breakdown from higher current, longer pulses are needed.

For the perpendicular STT MRAM, the switching time is largely determined by the thermal stability Δ as well as the write current.<ref>{{cite journal |last1=Khvalkovskiy |first1=A.V. |last2=Apalkov |first2=D. |last3=Watts |first3=S.|last4=Chepulskii |first4=R.|last5=Beach |first5=R S.|last6=Ong |first6=A.|last7=Tang |first7=X.|last8=Driskill-Smith |first8=A.|last9=Butler |first9=W.H.|last10=Visscher |first10=P.B.|last11=Lottis |first11=D.|last12=Chen |first12=E.|last13=Nikitin |first13=V.|last14=Krounbi |first14=M.|title=Basic principles of STT-MRAM cell operation in memory arrays |journal=Journal of Physics D: Applied Physics |volume=46 |issue=7 |pages=074001 |year=2013 |doi=10.1088/0022-3727/46/7/074001 |bibcode=2013JPhD...46g4001K |s2cid=110519121 }}</ref> A larger Δ (better for data retention) would require a larger write current or a longer pulse. A combination of high speed and adequate retention is only possible with a sufficiently high write current.

The only current memory technology that easily competes with MRAM in terms of performance at comparable density is [[static random-access memory]] (SRAM). SRAM consists of a series of transistors arranged in a [[flip-flop (electronics)|flip-flop]], which will hold one of two states as long as power is applied. Since the transistors have a very low power requirement, their switching time is very low. However, since an SRAM cell consists of several transistors, typically four or six, its density is much lower than DRAM. This makes it expensive, which is why it is used only for small amounts of high-performance memory, notably the [[CPU cache]] in almost all modern [[central processing unit]] designs.

Although MRAM is not quite as fast as SRAM, it is close enough to be interesting even in this role. Given its much higher density, a CPU designer may be inclined to use MRAM to offer a much larger<!-- smaller? --> but somewhat slower cache, rather than a smaller<!-- larger? --> but faster one. It remains to be seen how this trade-off will play out in the future.

===Endurance===
The endurance of MRAM is affected by write current, just like retention and speed, as well as read current. When the write current is sufficiently large for speed and retention, the probability of MTJ breakdown needs to be considered.<ref>{{Cite journal|title=Electric breakdown in ultra-thin MgO tunnel barrier junctions for spin-transfer torque switching|year=2009|doi=10.1063/1.3272268|arxiv=0907.3579|last1=Schäfers|first1=M.|last2=Drewello|first2=V.|last3=Reiss|first3=G.|last4=Thomas|first4=A.|last5=Thiel|first5=K.|last6=Eilers|first6=G.|last7=Münzenberg|first7=M.|last8=Schuhmann|first8=H.|last9=Seibt|first9=M.|journal=Applied Physics Letters|volume=95|issue=23|pages=232119|bibcode=2009ApPhL..95w2119S|s2cid=119251634}}</ref> If the read current/write current ratio is not small enough, read disturb becomes more likely, i.e., a read error occurs during one of the many switching cycles. The read disturb error rate is given by
:<math>1-\exp\left(-\frac{t_{read}}{\tau \exp(\Delta(1-I_{read}/I_{crit})}\right)</math>,

where τ is the relaxation time (1 ns) and I<sub>crit</sub> is the critical write current.<ref>{{cite book |first1=R. |last1=Bishnoi |first2=M. |last2=Ebrahimi |first3=F. |last3=Oboril |first4=M.B. |last4=Tahoori |chapter=Read disturb fault detection in STT-MRAM |title=2014 International Test Conference |year=2014 |isbn= 978-1-4799-4722-5|pages=1–7 |doi=10.1109/TEST.2014.7035342|s2cid=7957290 }}</ref> Higher endurance requires a sufficiently low <math>I_{read}/I_{crit}</math>. However, a lower I<sub>read</sub> also reduces read speed.<ref>{{cite journal |first1=M. |last1=Chang |first2=S. |last2=Shen |first3=C. |last3=Liu |first4=C. |last4=Wu |first5=Y. |last5=Lin |first6=Y. |last6=King |first7=C. |last7=Lin |first8=H. |last8=Liao |first9=Y. |last9=Chih |first10=H. |last10=Yamauchi |title=An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory |journal=IEEE Journal of Solid-State Circuits |volume=48 |issue=3 |pages=864–877 |date=March 2013 |doi=10.1109/JSSC.2012.2235013 |bibcode=2013IJSSC..48..864C |s2cid=23020634 |url=}}</ref>

Endurance is mainly limited by the possible breakdown of the thin MgO layer.<ref>{{Cite web|url=https://www.linkedin.com/pulse/breakdown-limited-write-time-windows-stt-mram-frederick-chen|title=Breakdown-Limited Write Time Windows for STT-MRAM|website=www.linkedin.com}}</ref><ref>J. H. Lim et al., "Investigating the Statistical-Physical Nature of MgO Dielectric Breakdown in STT-MRAM at Different Operating Conditions," IEDM 2018.</ref>

===Overall===
MRAM has similar performance to SRAM, enabled by the use of sufficient write current. However, this dependence on write current also makes it a challenge to compete with the higher density comparable to mainstream DRAM and Flash. Nevertheless, some opportunities for MRAM exist where density need not be maximized. From a fundamental physics point of view, the spin-transfer torque approach to MRAM is bound to a "rectangle of death" formed by retention, endurance, speed, and power requirements, as covered above.

{| class="wikitable"
|-
! Design parameter level
! Retention
! Endurance
! Speed
! Power
|-
| High write current
| +
| − (breakdown)
| +
| −
|-
| Low write current
| −
| − (read disturb)
| −
| +
|-
| High Δ
| +
| − (breakdown)
| −
| − (higher current)
|-
| Low Δ
| −
| − (read disturb)
| +
| + (lower current)
|}

While the power-speed tradeoff is universal for electronic devices, the endurance-retention tradeoff at high current and the degradation of both at low Δ is problematic. Endurance is largely limited to 10<sup>8</sup> cycles.<ref>{{cite web | url=http://www.electronicdesign.com/industrial-automation/unleashing-mram-persistent-memory | title=StackPath | date=21 March 2018 }}</ref>

===Alternatives to MRAM===
Flash and EEPROM's limited write-cycles are a serious problem for any real RAM-like role. In addition, the high power needed to write the cells is a problem in low-power nodes, where non-volatile RAM is often used. The power also needs time to be "built up" in a device known as a [[charge pump]], which makes writing dramatically slower than reading, often as low as 1/1000 as fast. While MRAM was certainly designed to address some of these issues, a number of other new memory devices are in production or have been proposed to address these shortcomings.

To date, the only similar system to enter widespread production is [[ferroelectric RAM]], or F-RAM (sometimes referred to as FeRAM).

Also seeing renewed interest are silicon-oxide-nitride-oxide-silicon ([[SONOS]]) memory and [[ReRAM]]. [[3D XPoint]] has also been in development, but is known to have a higher power budget than DRAM.<ref>{{Cite web|url=https://www.tomshardware.com/news/intel-xd-xpoint-dimm-lenovo-thinksystem,36573.html|title=Lenovo Dishes On 3D XPoint DIMMS, Apache Pass In ThinkSystem SD650|first=Paul Alcorn 26|last=February 2018|website=Tom's Hardware|date=26 February 2018}}</ref>