Editing Network interface controller (section)

== Implementation ==
[[File:12 early PC network cards.jpg|thumb|12 early ISA 8 bit and 16 bit PC network cards. The lower right-most card is an early wireless network card, and the central card with partial beige plastic cover is a PSTN [[modem]].]]
[[File:Intel Ophir 82571 Dual Port Gigabit Ethernet Controller Die Shot.png|thumb|Intel Ophir 82571 dual-port Gigabit Ethernet controller [[Die (integrated circuit)|die]]]]
Network controllers were originally implemented as expansion cards that plugged into a computer bus. The low cost and ubiquity of the Ethernet standard means that most new computers have a network interface controller built into the motherboard. Newer [[Server (computing)|server]] motherboards may have multiple network interfaces built-in. The Ethernet capabilities are either [[Integrated circuit|integrated]] into the motherboard [[chipset]] or implemented via a low-cost dedicated Ethernet chip. A separate network card is typically no longer required unless additional independent network connections are needed or some non-Ethernet type of network is used. A general trend in computer hardware is towards [[System on a chip|integrating the various components of systems on a chip]], and this is also applied to network interface cards.

An Ethernet network controller typically has an [[8P8C]] socket where the network cable is connected. Older NICs also supplied [[BNC connector|BNC]], or [[Attachment Unit Interface|AUI]] connections. Ethernet network controllers typically support 10&nbsp;[[Mbit/s]] Ethernet, [[Fast Ethernet|100&nbsp;Mbit/s Ethernet]], and [[Gigabit Ethernet|{{nowrap|1000 Mbit/s}} Ethernet]] varieties. Such controllers are designated as ''[[10/100/1000]]'', meaning that they can support data rates of 10, 100 or {{nowrap|1000 Mbit/s}}. [[10 Gigabit Ethernet]] NICs are also available, and, {{As of|2014|11|lc=yes}}, are beginning to be available on [[computer motherboard]]s.<ref>{{cite web |url=http://www.networkcomputing.com/networking/will-2014-be-the--year-of-10-gigabit-ethernet/a/d-id/1234640? |title=Will 2014 Be The Year Of 10 Gigabit Ethernet? |author=Jim O'Reilly |publisher=Network Computing |date=2014-01-22 |access-date=2015-04-29}}</ref><ref>{{cite web |url=http://www.asrock.com/news/index.asp?id=2517 |title=Breaking Speed Limits with ASRock X99 WS-E/10G and Intel 10G BASE-T LANs |website=asrock.com |date=24 November 2014 |access-date=19 May 2015}}</ref>

[[File:Qle3442-cu 10gbe nic.jpg|thumb|A [[Qlogic]] QLE3442-CU SFP+ dual-port NIC]]
Modular designs like [[Small form-factor pluggable transceiver|SFP and SFP+]] are highly popular, especially for [[fiber-optic communication]]. These define a standard receptacle for media-dependent transceivers, so users can easily adapt the network interface to their needs.

[[LED]]s adjacent to or integrated into the network connector inform the user of whether the network is connected, and when data activity occurs.

The NIC may include [[ROM]] to store its factory-assigned [[MAC address]].<ref>{{cite web |url=https://www.itprotoday.com/cloud-computing/how-can-i-change-network-adapter-cards-mac-address |title=How can I change a network adapter card's MAC address? |author=John Savill |date=Nov 12, 2000 |access-date=2023-11-06}}</ref>

The NIC may use one or more of the following techniques to indicate the availability of packets to transfer:
* [[Polling (computer science)|Polling]] is where the [[CPU]] examines the status of the [[peripheral]] under program control.
* [[Interrupt request|Interrupt]]-driven I/O is where the peripheral alerts the CPU that it is ready to transfer data.

NICs may use one or more of the following techniques to transfer packet data:
* [[Programmed input/output]], where the CPU moves the data to or from the NIC to memory.
* [[Direct memory access]] (DMA), where a device other than the CPU assumes control of the [[system bus]] to move data to or from the NIC to memory. This removes load from the CPU but requires more logic on the card. In addition, a packet buffer on the NIC may not be required and [[latency (engineering)|latency]] can be reduced.