Editing Numerically controlled oscillator (section)

==Phase accumulator==
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A binary phase accumulator consists of an N-bit binary [[adder (electronics)|adder]] and a [[hardware register|register]] configured as shown in Figure 1.<ref name="Grzeg"/> Each clock cycle produces a new N-bit output consisting of the previous output obtained from the register summed with the frequency control word (FCW) which is constant for a given output frequency. The resulting output waveform is a staircase with step size <math>\Delta F</math>, the integer value of the FCW.<ref name="ADI"/> In some configurations, the phase output is taken from the output of the register which introduces a one clock cycle [[latency (engineering)|latency]] but allows the adder to operate at a higher clock rate.<ref name="latticeSC"/> 
[[Image:Phase Accum Graph.png|frame|Figure 2: Normalized phase accumulator output]]

The adder is designed to overflow when the sum of the [[absolute value]] of its operands exceeds its capacity (2<sup>N</sup>−1). The overflow bit is discarded so the output word width is always equal to its input word width. The remainder <math>\phi _n</math>, called the residual, is stored in the register and the cycle repeats, starting this time from <math>\phi _n</math> (see figure 2).<ref name="Grzeg"/> Since a phase accumulator is a [[finite-state machine]], eventually the residual at some sample K must return to the initial value <math>\phi _0</math>. The interval K is referred to as the grand repetition rate (GRR) given by 
:<math>\mbox{GRR}=\frac{2^N}{\mbox{GCD}(\Delta F,2^N)}</math>

where GCD is the [[greatest common divisor]] function. The GRR represents the true periodicity for a given <math>\Delta F</math> which for a high resolution NCO can be very long.<ref name="Grzeg"/> Usually we are more interested in the ''operating frequency'' determined by the average overflow rate, given by<ref name="ADI">{{citation |last1=Murphy |first1=Eva |last2=Slattery |first2=Colm |url=http://www.analog.com/library/analogdialogue/archives/38-08/dds.html |title=All About Direct Digital Synthesis |journal=Analog Dialogue |volume=38 |date=August 2004 |publisher=Analog Devices}}</ref>
 
:<math>F_{out} = \frac{\Delta F}{2^N}F_{clock} </math> &nbsp; &nbsp; &nbsp;(1)

The ''frequency resolution'', defined as the smallest possible incremental change in frequency, is given by<ref name="ADI"/>
:<math>F_{res} = \frac{F_{clock}}{2^N}</math> &nbsp; &nbsp; &nbsp;(2)

Equation (1) shows that the phase accumulator can be thought of as a programmable non-integer [[frequency divider]] of divide ratio <math>\Delta F/2^N</math>.<ref name= "kroupa"/>