Editing PCI-X (section)

===Background and motivation===
[[File:dualportintelmtpro1000mtserveradapterspc.jpg|thumb|A Dual Port [[Gigabit Ethernet]] [[Network Card]] for single PCI-X slot to save on PCI-X slots and use the full potential of the PCI-X [[64-bit computing|64-bit]] bus.]]
[[File:LSI Logic MegaRAID SATA 300-8X SATA RAID controller.jpg|thumb|A 8 port [[SATA]] [[host bus adapter]] for PCI-X from [[Lsi logic]].]]
[[File:HP VISUALIZE fx10 Pro (A1299-6503) front.jpg|thumb|HP VISUALIZE fx10 Pro [[video card]] for PCI-X]]
In PCI, a transaction that cannot be completed immediately is postponed by either the target or the initiator issuing retry-cycles, during which no other agents can use the PCI bus. Since PCI lacks a split-response mechanism to permit the target to return data at a later time, the bus remains occupied by the target issuing retry-cycles until the read data is ready. In PCI-X, after the master issues the request, it disconnects from the PCI bus, allowing other agents to use the bus. The split-response containing the requested data is generated only when the target is ready to return all of the requested data. Split-responses increase bus efficiency by eliminating retry-cycles, during which no data can be transferred across the bus.

PCI also suffered from the relative scarcity of unique interrupt lines. With only 4 interrupt pins (INT A/B/C/D), systems with many PCI devices require multiple functions to share an interrupt line, complicating host-side interrupt-handling. PCI-X added [[Message Signaled Interrupts]], an interrupt system using writes to host-memory. In MSI-mode, the function's interrupt is not signaled by asserting an INTx line. Instead, the function performs a memory-write to a system-configured region in host-memory. Since the content and address are configured on a per-function basis, MSI-mode interrupts are dedicated instead of shared. A PCI-X system allows both MSI-mode interrupts and legacy INTx interrupts to be used simultaneously (though not by the same function).

The lack of registered I/Os limited PCI to a maximum frequency of 66&nbsp;MHz. PCI-X I/Os are registered to the PCI clock, usually through means of a PLL to actively control I/O delay the bus pins. The improvement in setup time allows an increase in frequency to 133&nbsp;MHz.

Some devices, most notably Gigabit Ethernet cards, SCSI controllers (Fibre Channel and Ultra320), and cluster interconnects could by themselves saturate the PCI bus's 133&nbsp;MB/s bandwidth. Ports using a bus speed doubled to 66&nbsp;MHz and a bus width doubled to 64&nbsp;bits (with the pin count increased to 184 from 124), in combination or not, have been implemented. These extensions were loosely supported as optional parts of the PCI&nbsp;2.x standards, but device compatibility beyond the basic 133&nbsp;MB/s continued to be difficult.

Developers eventually used the combined 64-bit and 66-MHz extension as a foundation, and, anticipating future needs, established 66-MHz and 133-MHz variants with a maximum bandwidth of 532&nbsp;MB/s and 1064&nbsp;MB/s respectively. The joint result was submitted as PCI-X to the [[PCI-SIG|PCI Special Interest Group]] ([[Special Interest Group]] of the [[Association for Computing Machinery]]). Subsequent approval made it an [[open standard]] adoptable by all computer developers. The PCI SIG controls technical support, training, and compliance testing for PCI-X. IBM, Intel, Microelectronics, and [[Mylex]] were to develop supporting chipsets. [[3Com]] and [[Adaptec]] were to develop compatible peripherals. To accelerate PCI-X adoption by the industry, Compaq offered PCI-X development tools at their Web site.