Editing Page table (section)

== The translation process ==
[[File:Page table actions.svg|thumb|right|upright=2|Actions taken upon a virtual to physical address translation. Each translation is restarted if a TLB miss occurs, so that the lookup can occur correctly through hardware.]]

The [[memory management unit]] (MMU) inside the CPU stores a cache of recently used mappings from the operating system's page table. This is called the [[translation lookaside buffer]] (TLB), which is an associative cache.

When a virtual address needs to be translated into a physical address, the TLB is searched first. If a match is found, which is known as a ''TLB hit'', the physical address is returned and memory access can continue. However, if there is no match, which is called a ''TLB miss'', the MMU, the system firmware, or the operating system's TLB miss handler will typically look up the address mapping in the page table to see whether a mapping exists, which is called a ''page walk''. If one exists, it is written back to the TLB, which must be done because the hardware accesses memory through the TLB in a virtual memory system, and the faulting instruction is restarted, which may happen in parallel as well. The subsequent translation will result in a TLB hit, and the memory access will continue.