Editing Partial-response maximum-likelihood (section)

== Implementation in products ==
[[File:PRML chronology circa 1994 (scanned Nov 1, 2019).pdf|thumb|Early PRML chronology (created around 1994)]]
The first two implementations were in Tape (Ampex - 1984) and then in hard disk drives (IBM - 1990). Both are significant milestones with the [[Ampex]] implementation focused on very high data-rate for a digital instrumentation recorder and [[IBM]] focused on a high level of integration and low power consumption for a mass-market HDD. In both cases, the initial equalization to PR4 response was done with analog circuitry but the Viterbi algorithm was performed with digital logic. In the tape application, PRML superseded 'flat equalization'. In the HDD application, PRML superseded [[run-length limited|RLL]] codes with 'peak detection'.

=== Tape recording ===
The first implementation of PRML was shipped in 1984 in the Ampex Digital Cassette Recording System (DCRS). The chief engineer on DCRS was [[Charles Coleman (engineer)|Charles Coleman]]. The machine evolved from a 6-head, transverse-scan, digital [[video tape recorder]]. DCRS was a cassette-based, digital, instrumentation recorder capable of extended play times at very high data-rate.<ref>T. Wood, "[http://www.thic.org/pdf/Oct96/ampex.twood.pdf Ampex Digital Cassette Recording System (DCRS)]", THIC meeting, Ellicott City, MD, 16 Oct., 1996 (PDF)</ref> It became Ampex' most successful digital product.<ref>R. Wood, K. Hallamasek, "[https://www.computerhistory.org/collections/catalog/102788145 Overview of the prototype of the first commercial PRML channel]", Computer History Museum, #102788145, Mar. 26, 2009</ref>

The heads and the read/write channel ran at the (then) remarkably high data-rate of 117&nbsp;Mbit/s.<ref>C. Coleman, D. Lindholm, D. Petersen, and R. Wood, "[https://web.archive.org/web/20191007051735/https://ieeexplore.ieee.org/document/5261308 High Data Rate Magnetic Recording in a Single Channel]", J. IERE, Vol., 55, No. 6, pp. 229-236, June 1985. (invited) (Charles Babbage Award for Best Paper)</ref> The PRML electronics were implemented with four 4-bit, [[Plessey]] [[analog-to-digital converter]]s (A/D) and [https://en.wikichip.org/wiki/fairchild/100k 100k ECL logic].<ref>Computer History Museum, #102741157, "[https://www.computerhistory.org/collections/catalog/102741157 Ampex PRML Prototype Circuit]", circa 1982</ref> The PRML channel outperformed a competing implementation based on "Null-Zone Detection".<ref>J. Smith, "[https://ieeexplore.ieee.org/document/1089924 Error Control in Duobinary Data Systems by Means of Null Zone Detection]", IEEE Trans. Comm., Vil 16, No. 6, pp. 825-830, Dec., 1968</ref> A prototype PRML channel was implemented earlier at 20&nbsp;Mbit/s on a prototype 8-inch HDD,<ref name=8inch>R. Wood, S. Ahlgrim, K. Hallamasek, R. Stenerson, "[https://ieeexplore.ieee.org/document/1063460 An Experimental Eight-inch Disc Drive with One-hundred Megabytes Per Surface]", IEEE Trans. Mag., vol. MAG-20, No. 5, pp. 698-702, Sept. 1984. (invited)</ref> but Ampex exited the HDD business in 1985. These implementations and their mode of operation are best described in a paper by Wood and Petersen.<ref>R. Wood and D. Petersen, "[https://ieeexplore.ieee.org/document/1096563 Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel]", IEEE Trans. Comm., Vol., COM-34, No. 5, pp. 454-461, May 1986 (invited)</ref> Petersen was granted a patent on the PRML channel but it was never leveraged by Ampex.<ref>D. Petersen, "[https://patents.google.com/patent/US4504872A/en Digital maximum likelihood detector for class IV partial response]", US Patent 4504872, filed Feb. 8, 1983</ref>

=== Hard disk drives ===
In 1990, IBM shipped the first PRML channel in an HDD in the [[History of IBM magnetic disk drives#IBM 0681|IBM 0681]] It was full-height 5¼-inch form-factor with up to 12 of 130&nbsp;mm disks and had a maximum capacity of 857&nbsp;MB.

The PRML channel for the IBM 0681 was developed in [[IBM Rochester]] lab. in Minnesota<ref>J. Coker, R. Galbraith, G. Kerwin, J. Rae, P. Ziperovich, "[https://ieeexplore.ieee.org/document/278677 Implementation of PRML in a rigid disk drive]", IEEE Trans. Magn., Vol. 27, No. 6, pp. 4538-43, Nov. 1991</ref> with support from the [[IBM Zurich]] Research lab. in [[Switzerland]].<ref>R.Cidecyan, F.Dolvio, R. Hermann, W.Hirt, W. Schott "[https://ieeexplore.ieee.org/document/124468 A PRML System for Digital Magnetic Recording]", IEEE Journal on Selected Areas in Comms, vol.10, No.1, pp.38-56, Jan 1992</ref> A parallel R&D effort at IBM San Jose did not lead directly to a product.<ref>T. Howell, et al. "[https://ieeexplore.ieee.org/document/104703 Error Rate Performance of Experimental Gigabit per Square Inch Recording Components]", IEEE Trans. Magn., Vol. 26, No. 5, pp. 2298-2302, 1990</ref> A competing technology at the time was 17ML<ref>A. Patel, "[https://www.researchgate.net/publication/224663211 Performance Data for a Six-Sample Look-Ahead 17ML Detection Channel]", IEEE Trans. Magn., Vol. 29, No. 6, pp. 4012-4014, Dec. 1993</ref> an example of Finite-Depth Tree-Search (FDTS).<ref>R. Carley, J. Moon, "[https://patents.google.com/patent/US5136593A/en Apparatus and method for fixed delay tree search]", filed Oct. 30th, 1989</ref><ref>R. Wood, "[https://ieeexplore.ieee.org/document/42527 New Detector for 1,k Codes Equalized to Class II Partial Response]", IEEE Trans. Magn., Vol. MAG-25, No. 5, pp. 4075-4077, Sept. 1989</ref>

The IBM 0681 read/write channel ran at a data-rate of 24&nbsp;Mbit/s but was more highly integrated with the entire channel contained in a single 68-pin [[Plastic leaded chip carrier|PLCC]] [[integrated circuit]] operating off a 5 volt supply. As well as the fixed analog equalizer, the channel boasted a simple adaptive digital ''cosine equalizer''<ref>T. Kameyama, S. Takanami, R. Arai, "[https://ieeexplore.ieee.org/document/1059216 Improvement of recording density by means of cosine equalizer]", IEEE Trans. Magn., Vol. 12, No. 6, pp. 746-748, Nov. 1976</ref> after the A/D to compensate for changes in radius and/or changes in the magnetic components.

=== Write precompensation ===
The presence of nonlinear transition-shift (NLTS) distortion on [[Non-return-to-zero|NRZ]] recording at high density and/or high data-rate was recognized in 1979.<ref>R. Wood, R. Donaldson, "[https://ieeexplore.ieee.org/document/1060300 The Helical-Scan Magnetic Tape Recorder as a Digital Communication Channel]", IEEE Trans. Mag. vol. MAG-15, no. 2, pp. 935-943, March 1979</ref> The magnitude and sources of NLTS can be identified using the 'extracted dipulse' technique.<ref>D. Palmer, P. Ziperovich, R. Wood, T. Howell, "[https://ieeexplore.ieee.org/document/1065310 Identification of Nonlinear Write Effects Using Pseudo-Random Sequences]", IEEE Trans. Magn., Vol. MAG-23, no. 5, pp. 2377-2379, Sept. 1987</ref><ref>D. Palmer, J. Hong, D. Stanek, R. Wood, "[https://ieeexplore.ieee.org/document/5680698/ Characterization of the Read/Write Process for Magnetic Recording]", IEEE Trans. Magn., Vol. MAG-31, No. 2, pp. 1071-1076, Mar. 1995 (invited)</ref>

Ampex was the first to recognize the impact of NLTS on PR4.<ref>P. Newby, R. Wood, "[https://ieeexplore.ieee.org/document/1064566 The Effects of Nonlinear Distortion on Class IV Partial Response]", IEEE Trans. Magn., Vol. MAG-22, No. 5, pp. 1203-1205, Sept. 1986</ref> and was first to implement [[Write precompensation]] for PRML NRZ recording. 'Precomp.' largely cancels the effect of NLTS.<ref name=8inch /> Precompensation is viewed as a necessity for a PRML system and is important enough to appear in the [[BIOS]] HDD setup<ref>{{Cite web |url=http://www.kva.kursk.ru/bios1/HTML1/standard.html |title=Kursk: BIOS Settings - Standard CMOS Setup, Feb 12, 2000 |access-date=October 8, 2019 |archive-date=October 4, 2018 |archive-url=https://web.archive.org/web/20181004103524/http://www.kva.kursk.ru/bios1/HTML1/standard.html |url-status=dead }}</ref> although it is now handled automatically by the HDD.