Editing Physical Address Extension (section)

== Design ==
With PAE, the [[page table entry]] of the x86 architecture is enlarged from 32 to 64 bits. This allows more room for the physical page address, or "page frame number" field, in the page table entry. In the initial implementations of PAE the page frame number field was expanded from 20 to 24 bits. The size of the "byte offset" from the address being translated is still 12 bits, so total physical address size increases from 32&nbsp;bits to 36&nbsp;bits (i.e. from 20+12 to 24+12). This increased the physical memory that is theoretically addressable by the CPU from 4&nbsp;GB to 64&nbsp;GB.

In the first processors that supported PAE, support for larger physical addresses is evident in their package pinout, with address pin designations going up to A35 instead of stopping at A31.<ref>{{cite book|title=Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet | publisher=Intel Corporation |publication-date=February 2000 |id=245094-002 |quote=A[35:03]# (I/O): The A[35:3]# (Address) signals define a 2-to-the-36-byte physical memory address space.  |page=86 }}</ref> Later processor families use interconnects such as [[Hypertransport]] or [[QuickPath Interconnect]], which lack dedicated memory address signals, so this relationship is less apparent.

The 32-bit size of the virtual address is not changed, so regular application software continues to use instructions with 32-bit addresses and (in a [[flat memory model]]) is limited to 4&nbsp;gigabytes of virtual address space. Operating systems supporting this mode use [[page table]]s to map the regular 4&nbsp;GB virtual address space into the physical memory, which, depending on the operating system and the rest of the hardware platform, may be as big as 64&nbsp;GB. The mapping is typically applied separately for each [[Process (computing)|process]], so that the additional RAM is useful even though no single process can access it all simultaneously.

Later work associated with AMD's development of [[x86-64]] architecture expanded the theoretical possible size of physical addresses to 52 bits.<ref name="amd-24593"/>{{rp|page=24|date=July 2023}}