Editing Planar process (section)

==History==
===Development===
In 1955 at [[Bell Labs]], [[Carl Frosch]] and Lincoln Derick accidentally grew a layer of silicon dioxide over a silicon wafer, for which they observed [[Passivation (chemistry)|surface passivation]] properties.<ref name=":02">{{Cite journal |last1=Huff |first1=Howard |last2=Riordan |first2=Michael |date=2007-09-01 |title=Frosch and Derick: Fifty Years Later (Foreword) |url=https://iopscience.iop.org/article/10.1149/2.F02073IF |journal=The Electrochemical Society Interface |volume=16 |issue=3 |pages=29 |doi=10.1149/2.F02073IF |issn=1064-8208|url-access=subscription }}</ref><ref>{{Cite patent|number=US2802760A|title=Oxidation of semiconductive surfaces for controlled diffusion|gdate=1957-08-13|invent1=Lincoln|invent2=Frosch|inventor1-first=Derick|inventor2-first=Carl J.|url=https://patents.google.com/patent/US2802760A}}</ref> In 1957, Frosch and Derick were able to manufacture the first silicon dioxide field effect transistors, the first transistors in which drain and source were adjacent at the surface, showing that silicon dioxide surface passivation protected and insulated silicon wafers.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> 

At Bell Labs, the importance of Frosch's technique was immediately realized. Results of their work circulated around Bell Labs in the form of BTL memos before being published in 1957. At [[Shockley Semiconductor Laboratory|Shockley Semiconductor]], Shockley had circulated the preprint of their article in December 1956 to all his senior staff, including [[Jean Hoerni]].<ref name="Moskowitz">{{cite book |last1=Moskowitz |first1=Sanford L. |url=https://books.google.com/books?id=2STRDAAAQBAJ&pg=PA168 |title=Advanced Materials Innovation: Managing Global Technology in the 21st century |date=2016 |publisher=[[John Wiley & Sons]] |isbn=978-0-470-50892-3 |page=168}}</ref><ref>{{cite book |author1=Christophe Lécuyer |url=https://books.google.com/books?id=LaZpUpkG70QC&pg=PA62 |title=Makers of the Microchip: A Documentary History of Fairchild Semiconductor |author2=David C. Brook |author3=Jay Last |date=2010 |publisher=MIT Press |isbn=978-0-262-01424-3 |pages=62–63}}</ref><ref>{{cite book |last1=Claeys |first1=Cor L. |url=https://books.google.com/books?id=bu22JNYbE5MC&pg=PA27 |title=ULSI Process Integration III: Proceedings of the International Symposium |date=2003 |publisher=[[The Electrochemical Society]] |isbn=978-1-56677-376-8 |pages=27–30}}</ref><ref name="Lojek120">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=120}}</ref> Later, Hoerni attended a meeting where [[Mohamed M. Atalla|Atalla]] presented a paper about passivation based on the previous results at Bell Labs.<ref name="Lojek120" /> Taking advantage of silicon dioxide's passivating effect on the silicon surface, Hoerni proposed to make transistors that were protected by a layer of silicon dioxide.<ref name="Lojek120" /> 

Jean Hoerni, while working at [[Fairchild Semiconductor]], had first patented the planar process in 1959.<ref>{{patent|US|3025589|Hoerni, J. A.: "Method of Manufacturing Semiconductor Devices” filed May 1, 1959}}</ref><ref>{{patent|US|3064167|Hoerni, J. A.: "Semiconductor device" filed May 15, 1960}}</ref> K. E. Daburlos and H. J. Patterson of Bell Laboratories continued on the work of C. Frosch and L. Derick, and developed a process similar to Hoerni’s about the same time.<ref name="Lojek120" /> Together with the use of metallization (to join together the integrated circuits), and the concept of [[p–n junction isolation]] (from [[Kurt Lehovec]]), the researchers at Fairchild were able to create circuits on a single silicon crystal slice (a wafer) from a [[monocrystalline silicon]] [[Boule (crystal)|boule]].

In 1959, [[Robert Noyce]] built on Hoerni's work with his conception of an [[integrated circuit]] (IC), which added a layer of metal to the top of Hoerni's basic structure to connect different components, such as transistors, [[capacitors]], or [[resistors]], located on the same piece of silicon. The planar process provided a powerful way of implementing an integrated circuit that was superior to earlier conceptions of the integrated circuit.<ref name="Bassett46">{{cite book|last1=Bassett|first1=Ross Knox|url=https://books.google.com/books?id=UUbB3d2UnaAC&pg=PA46|title=To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology|date=2007|publisher=[[Johns Hopkins University Press]]|isbn=9780801886393|page=46}}</ref> Noyce's invention was the first monolithic IC chip.<ref>{{cite web |title=1959: Practical Monolithic Integrated Circuit Concept Patented |url=https://www.computerhistory.org/siliconengine/practical-monolithic-integrated-circuit-concept-patented/ |website=[[Computer History Museum]] |accessdate=13 August 2019}}</ref><ref>{{cite web |title=Integrated circuits |url=https://www.hq.nasa.gov/alsj/ic-pg3.html |website=[[NASA]] |accessdate=13 August 2019}}</ref>

Early versions of the planar process used a [[photolithography]] process using near-ultraviolet light from a mercury vapor lamp.
As of 2011, small features are typically made with 193&nbsp;nm "deep" UV lithography.<ref>
Shannon Hill. [https://www.nist.gov/pml/div685/extreme-uv-lithography.cfm "UV Lithography: Taking Extreme Measures"]. National Institute of Standards and Technology (NIST).</ref> As of 2022, the [[ASML Holding|ASML]] NXE platform uses 13.5&nbsp;nm extreme ultraviolet (EUV) light, generated by a tin-based plasma source, as part of the [[extreme ultraviolet lithography]] process.