Editing Programmable logic device (section)

== PLA <span class="anchor" id="Programmable logic array"></span><span class="anchor" id="PLA"></span><span class="anchor" id="Programmable logic sequencer"></span><span class="anchor" id="PLS"></span>==
{{main|Programmable logic array}}

In 1970, [[Texas Instruments]] developed a mask-programmable IC based on the [[IBM]] read-only associative memory or ROAM. This device, the TMS2000, was programmed by altering the metal layer during the production of the IC. The TMS2000 had up to 17 inputs and 18 outputs with 8 [[JK flip-flops]] for memory. TI coined the term [[programmable logic array]] for this device.<ref name = "TI PLA 1970" />

A programmable logic array (PLA) has a programmable AND gate array, which links to a programmable OR gate array, which can then be conditionally complemented to produce an output. A PLA is similar to a ROM concept, however a PLA does not provide full decoding of a variable and does not generate all the [[minterms]] as in a ROM.

The programmable logic sequencer (PLS/FPLS) is similar to a PLA, but with integral registered outputs using a number of [[flip-flops]] to allow creation of some [[state machine]]s. [[Signetics]] introduced the first FPLS in 1979.<ref name="Alford 1989">{{cite book |last=Alford |first=Roger C.| title=Programmable Logic Designer's Guide |publisher=Howard W. Sams| date=1989 |pages=67–69 |isbn =0-672-22575-1 |url=https://archive.org/details/programmablelogi0000alfo/<!--|archive-url=https://archive.org/details/programmablelogi0000alfo/|archive-date=2022-10-11 -->|quote=The registers can be dynamically or permanently configured as D, J-K, or T flip-flops, because of the flexibility offered by the inclusion of the “M” inverters (M<sub>0</sub>-M<sub>5</sub>). The outputs of the registers are fed back into the AND-array ''before'' reaching the tri-state output buffers, allowing for Mealy and Moore state machine development.}}</ref>