Editing RapidIO (section)

=== Releases ===

The RapidIO specification revision 1.1 (3xN Gen1), released in March 2001, defined a wide, parallel bus. This specification did not achieve extensive commercial adoption.

The RapidIO specification revision 1.2, released in June 2002,<ref>{{cite web |url=http://www.rapidio.org/rapidio-specifications/#tab1752 |title=RapidIO Standard Revision 1.2 |author=<!--Staff writer(s); no by-line.--> |date=26 June 2002 |website=www.rapidio.org |publisher=RapidIO Trade Association |access-date=9 October 2014 |archive-date=24 December 2016 |archive-url=https://web.archive.org/web/20161224232948/http://www.rapidio.org/rapidio-specifications/#tab1752 |url-status=dead }}</ref> defined a serial interconnection based on the XAUI physical layer. Devices based on this specification achieved significant commercial success within wireless baseband,<ref>{{cite web |url=http://files.shareholder.com/downloads/IDTI/3533679921x0x500036/14BEEAA3-863E-41DD-9CB2-4F99279AC6EA/IDT_2011Annual_compositetotal.pdf |title=Integrated Device Technology 2011 Annual Report |author=<!--Staff writer(s); no by-line.--> |date=6 June 2011 |page=4 |website=www.idt.com |publisher=Integrated Device Technology Inc |access-date=9 October 2014 |archive-date=3 March 2016 |archive-url=https://web.archive.org/web/20160303213710/http://files.shareholder.com/downloads/IDTI/3533679921x0x500036/14BEEAA3-863E-41DD-9CB2-4F99279AC6EA/IDT_2011Annual_compositetotal.pdf |url-status=dead }}</ref> imaging and military computing.<ref>{{cite web |url=http://www.linleygroup.com/newsletters/newsletter_detail.php?num=5064 |title= RapidIO Reaches for the Clouds |author=Jag Bolaria |date=October 15, 2013 |website=www.linleygroup.com |publisher=The Linley Group |access-date=9 October 2014}}</ref>

The RapidIO specification revision 1.3 was released in June 2005.

The RapidIO specification revision 2.0 (6xN Gen2), was released in March 2008.<ref>{{cite web |url=http://www.rapidio.org/files/Rev2.0_stack2.zip |title=RapidIO Standard Revision 2.0 |author=<!--Staff writer(s); no by-line.--> |date=23 February 2005 |website=www.rapidio.org |publisher=RapidIO Trade Association |access-date=9 October 2014 |archive-date=2 December 2016 |archive-url=https://web.archive.org/web/20161202223414/http://www.rapidio.org/files/Rev2.0_stack2.zip |url-status=dead }}</ref> This added more port widths (2×, 8×, and 16×) and increased the maximum lane speed to 6.25&nbsp;[[Baud|GBd]] / 5&nbsp;Gbit/s.

The RapidIO specification revision 2.1 was released in September 2009.

The RapidIO specification revision 2.2 was released in May 2011.

The RapidIO specification revision 3.0 (10xN Gen3) released in October 2013.<ref>{{cite web |url=http://www.rapidio.org/rapidio-specifications/#tab1930 |title=RapidIO Standard Revision 3.0 |author=<!--Staff writer(s); no by-line.--> |date=10 November 2013 |website=www.rapidio.org |publisher=RapidIO Trade Association |access-date=9 October 2014 |archive-date=24 December 2016 |archive-url=https://web.archive.org/web/20161224232948/http://www.rapidio.org/rapidio-specifications/#tab1930 |url-status=dead }}</ref> The following changes were made:
* Based on industry-standard Ethernet 10GBASE-KR electrical specifications for short (20&nbsp;cm + connector) and long (1&nbsp;m + 2 connector) reach applications
* Directly leverages the Ethernet 10GBASE-KR DME training scheme for long-reach signal quality optimization
* Defines a 64b/67b encoding scheme (similar to the [[Interlaken (networking)|Interlaken]] standard) to support both [[Copper wire and cable|copper]] and [[Optical fiber cable|optical]] interconnects and to improve [[spectral efficiency|bandwidth efficiency]]
* Dynamic asymmetric links to save power (for example, 4× in one direction, 1× in the other)
* Addition of a time synchronization capability similar to [[Precision Time Protocol|IEEE 1588]], but much less expensive to implement
* Support for 32-bit device IDs, increasing maximum system size and enabling innovative hardware virtualization support
* Revised routing table programming model simplifies network management software
* Packet exchange protocol optimizations

The RapidIO specification revision 3.1, was released in October 2014.<ref>{{cite web |url=http://www.rapidio.org/wp-content/uploads/2014/10/RapidIO-3.1-Specification.pdf |title=RapidIO Standard Revision 3.1 |author=<!--Staff writer(s); no by-line.--> |date=13 October 2014 |website=www.rapidio.org |publisher=RapidIO Trade Association |access-date=18 October 2014 |archive-date=23 October 2014 |archive-url=https://web.archive.org/web/20141023025959/http://www.rapidio.org/wp-content/uploads/2014/10/RapidIO-3.1-Specification.pdf |url-status=dead }}</ref> It  was developed through a collaboration between the RapidIO Trade Association and NGSIS.  Revision 3.1 has the following changes compared to the 3.0 specification:
* MECS Time Synchronization protocol for smaller embedded systems.  MECS Time Synchronization supports redundant time sources.  This protocol is lower cost than the Timestamp Synchronization Protocol introduced in revision 3.0
* [[Pseudorandom binary sequence|PRBS]] test facilities and standard register interface.
* Structurally Asymmetric Link behavioral definition and standard register interface.  These structurally Asymmetric Links carry much more data in one direction than the other, for applications such as sensors or processing pipelines.  Unlike dynamic asymmetric links, Structurally Asymmetric Links allow implementers to remove lanes on boards and in silicon, saving size, weight, and power.  Structurally asymmetric links also allow the use of alternative lanes in the case of a hardware failure on a multi-lane port.
* Extended error log to capture a series of errors for diagnostic purposes
* Space device profiles for endpoints and switches, which define what it means to be a space-compliant RapidIO device.

The RapidIO specification revision 3.2 was released in February 2016.

The RapidIO specification revision 4.0 (25xN Gen4) was released in June 2016.<ref name="auto">{{cite web |url=http://www.rapidio.org/rapidio-specifications/#tab1277 |title=RapidIO Standard Revision 4.0 |author=<!--Staff writer(s); no by-line.--> |date=June 2016 |website=www.rapidio.org |publisher=RapidIO Trade Association |access-date=15 August 2016 |archive-date=24 December 2016 |archive-url=https://web.archive.org/web/20161224232948/http://www.rapidio.org/rapidio-specifications/#tab1277 |url-status=dead }}</ref> It had the following changes compared to the 3.x specifications:
* Support 25 Gbaud lane rate and physical layer specification, with associated programming model changes
* Allow IDLE3 to be used with any Baud Rate Class, with specified IDLE sequence negotiation
* Increased maximum packet size to 284 bytes in anticipation of Cache Coherency specification
* Support 16 physical layer priorities
* Support “Error Free Transmission” for high throughput isochronous information transfer

The RapidIO specification revision 4.1 was released in July 2017.<ref>{{cite web |url=https://www.vita.com/rapidio-specifications |title=RapidIO Standard Revision 4.1 |date=July 2017 |website=vita.com |publisher=RapidIO Trade Association |access-date=11 August 2019}}</ref>