Editing Reconfigurable computing (section)

==Theories==

===Tredennick's Classification===
{|class="wikitable" | align="right"
|+ ''Table 1: Nick Tredennick's Paradigm Classification Scheme''
|-
|bgcolor="#BBBBFF" colspan="2" | '''Early Historic Computers:'''
|-
|bgcolor="#BBBBFF" | &nbsp;
! Programming Source
|-
| Resources fixed
| none
|-
| Algorithms fixed
| none
|-
|bgcolor="#ffebad" colspan=2 | '''von Neumann Computer:'''
|-
|bgcolor="#ffebad" | &nbsp;
! Programming Source
|-
| Resources fixed
| none
|-
| Algorithms variable
| Software (instruction streams)
|-
|bgcolor="#ffbbbb" colspan="2"| '''Reconfigurable Computing Systems:'''
|-
|bgcolor="#ffbbbb"| &nbsp;
! Programming Source
|-
| Resources variable
| Configware (configuration)
|-
| Algorithms variable
| [[Flowware]] (data streams)
|}
The fundamental model of the reconfigurable computing machine paradigm, the data-stream-based [[anti machine]] is well illustrated by the differences to other machine paradigms that were introduced earlier, as shown by [[Nick Tredennick]]'s following classification scheme of computing paradigms (see "Table 1: Nick Tredennick's Paradigm Classification Scheme").<ref>N. Tredennick: The Case for Reconfigurable Computing; Microprocessor Report, Vol. 10 No. 10, 5 August 1996, pp 25–27.</ref>

===Hartenstein's Xputer===
{{main|Xputer}}
Computer scientist Reiner Hartenstein describes reconfigurable computing in terms of an ''[[anti-machine]]'' that, according to him, represents a fundamental paradigm shift away from the more conventional [[Von Neumann architecture|von Neumann machine]].<ref>Hartenstein, R. 2001. A decade of reconfigurable computing: a visionary retrospective. In ''Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2001)'' (Munich, Germany). W. Nebel and A. Jerraya, Eds. Design, Automation, and Test in Europe. IEEE Press, Piscataway, NJ, 642–649.</ref> Hartenstein calls it Reconfigurable Computing Paradox, that software-to-configware (software-to-[[FPGA]]) migration results in reported speed-up factors of up to more than four orders of magnitude, as well as a reduction in electricity consumption by up to almost four orders of magnitude—although the technological parameters of FPGAs are behind the [[Moore's law|Gordon Moore curve]] by about four orders of magnitude, and the clock frequency is substantially lower than that of microprocessors. This paradox is partly explained by the [[Von Neumann bottleneck|Von Neumann syndrome]].