Editing SIMM (section)

==30-pin SIMMs==
[[File:Atari STE 256kB RAM 1.jpg|thumbnail|30-pin SIMM, 256 KB capacity]]
[[File:SIMM Bank.jpg|thumbnail|Two 30-pin SIMM slots on an [[IBM PS/2 Model 50]] motherboard]]
Standard sizes: 256 KB, 1 MB, 4 MB, 16 MB.

30-pin SIMMs have 12 address lines, which can provide a total of 24 address bits. With an 8-bit data width, this leads to an absolute maximum capacity of 16&nbsp;MB for both parity and non-parity modules (the additional redundancy-bit chip usually does not contribute to the usable capacity).
{|class="wikitable"
|+ 30-pin SIMM
!Pin # !! Name !! Signal description
|rowspan=16|
!Pin # !! Name !! Signal description
|-
|1||V<sub>CC</sub>||+5 VDC
|16||DQ4||Data 4
|-
|2||/CAS||Column address strobe
|17||A8||Address 8
|-
|3||DQ0||Data 0
|18||A9||Address 9
|-
|4||A0||Address 0
|19||A10||Address 10
|-
|5||A1||Address 1
|20||DQ5||Data 5
|-
|6||DQ1||Data 1
|21||/WE||Write enable
|-
|7||A2||Address 2
|22||V<sub>SS</sub>||Ground
|-
|8||A3||Address 3
|23||DQ6||Data 6
|-
|9||V<sub>SS</sub>||Ground
|24||A11||Address 11
|-
|10||DQ2||Data 2
|25||DQ7||Data 7
|-
|11||A4||Address 4
|26||QP<sup>*</sup>||Data parity out
|-
|12||A5||Address 5
|27||/RAS||Row address strobe
|-
|13||DQ3||Data 3
|28||/CASP<sup>*</sup>||Parity column address strobe
|-
|14||A6||Address 6
|29||DP<sup>*</sup>||Data parity in
|-
|15||A7||Address 7
|30||V<sub>CC</sub>||+5 VDC
|}
<sup>*</sup> Pins 26, 28 and 29 are [[not connected]] on non-parity SIMMs.