Editing Serial Peripheral Interface (section)

===Data transmission===
[[File:SPI 8-bit circular transfer.svg|upright=1.8|thumb|A typical hardware setup using two [[shift register]]s to form an inter-chip [[circular buffer]] ]]
To begin communication, the SPI master first selects a slave device by pulling its {{Overline|SS}} low. (Note: the bar above {{Overline|SS}} indicates it is an [[active low]] signal, so a low voltage means "selected", while a high voltage means "not selected")

If a waiting period is required, such as for an analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.{{NoteTag|Some slaves require a falling edge of the {{Overline|Slave Select}} signal to initiate an action. An example is the Maxim MAX1242 ADC, which starts conversion on a high→low transition.}}

During each SPI clock cycle, full-duplex transmission of a single bit occurs. The master sends a bit on the MOSI line while the slave sends a bit on the MISO line, and then each reads their corresponding incoming bit. This sequence is maintained even when only one-directional data transfer is intended.

Transmission using a single slave involves one shift register in the master and one shift register in the slave, both of some given word size (e.g. 8 bits). The transmissions often consist of eight-bit words, but other word-sizes are also common, for example, sixteen-bit words for touch-screen controllers or audio codecs, such as the TSC2101 by Texas Instruments, or twelve-bit words for many digital-to-analog or analog-to-digital converters. 

Data is usually shifted out with the [[most-significant bit]] (MSB) first but the original specification has a LSBFE ("LSB-First Enable") to control whether data is transferred least (LSB) or most significant bit (MSB) first. On the clock edge, both master and slave shift out a bit to its counterpart. On the next clock edge, each receiver samples the transmitted bit and stores it in the shift register as the new least-significant bit. After all bits have been shifted out and in, the master and slave have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the master stops toggling the clock signal, and typically deselects the slave.

If a single slave device is used, its {{Overline|SS}} pin ''may'' be fixed to [[logic level|logic low]] if the slave permits it. With multiple slave devices, a [[#Multidrop configuration|multidrop configuration]] requires an independent {{Overline|SS}} signal from the master for each slave device, while a [[#Daisy chain configuration|daisy-chain configuration]] only requires one {{Overline|SS}} signal.

Every slave on the bus that has not been selected should disregard the input clock and MOSI signals. And to prevent [[Bus contention|contention]] on MISO, non-selected slaves must use [[Three-state logic|tristate]] output. Slaves that aren't already tristate will need external tristate buffers to ensure this.<ref name="Better SPI Bus Design in 3 Steps" />