Editing Source-synchronous (section)

=== Timing Analysis ===

[[Synchronous logic]] elements such as flip-flops have static timing criteria that must be satisfied in order for them to work correctly. In a system-synchronous clock topology where a skew-aligned clock is fed to all devices, the criteria are

<math>T_{clock} > T_{setup} + T_{ko} + T_{skew}</math>

A source-synchronous clock topology eliminates two of these factors, <math>T_{ko}</math> and <math>T_{skew}</math>. The former is eliminated since both clock and data signals are driven by identical flip-flops on the same silicon at the same temperature and voltage, thereby equalizing the <math>T_{ko}</math> seen by both clock and data. The latter is eliminated for the same reason - since the clock and data are driven by identical devices and (ideally) connected with wires of equal length, the skew between clock and data is greatly reduced. For this reason, <math>T_{clock}</math> can be reduced significantly. Since frequency is inversely proportional to clock period, the clock frequency increases as a result.