Editing Stack machine (section)

=== Stack storage ===
Some stack machines have a stack of limited size, implemented as a register file. The ALU will access this with an index. A large register file uses a lot of transistors and hence this method is only suitable for small systems. A few machines have both an expression stack in memory and a separate register stack. In this case, software, or an interrupt may move data between them. Some machines have a stack of unlimited size, implemented as an array in RAM, which is cached by some number of "top of stack" address registers to reduce memory access. Except for explicit "load from memory" instructions, the order of operand usage is identical with the order of the operands in the data stack, so excellent prefetching can be accomplished easily.

Consider {{code|X+1}}. It compiles to {{code|Load X}}; {{code|Load 1}}; {{code|Add}}. With a stack stored completely in RAM, this does implicit writes and reads of the in-memory stack:
* Load X, push to memory
* Load 1, push to memory
* Pop 2 values from memory, add, and push result to memory
for a total of 5 data cache references.

The next step up from this is a stack machine or interpreter with a single top-of-stack register. The above code then does:
* Load X into empty TOS register (if hardware machine) '''or''' Push TOS register to memory, Load X into TOS register (if interpreter)
* Push TOS register to memory, Load 1 into TOS register
* Pop left operand from memory, add to TOS register and leave it there
for a total of 3 data cache references, worst-case. Generally, interpreters don't track emptiness, because they don't have to—anything below the stack pointer is a non-empty value, and the TOS cache register is always kept hot. Typical Java interpreters do not buffer the top-of-stack this way, however, because the program and stack have a mix of short and wide data values.

If the hardwired stack machine has 2 or more top-stack registers, or a register file, then all memory access is avoided in this example and there is only 1 data cache cycle.