Editing Superscalar processor (section)

==Scalar to superscalar==
The simplest processors are scalar processors. Each instruction executed by a scalar processor typically manipulates one or two data items at a time. By contrast, each instruction executed by a [[vector processor]] operates simultaneously on many data items. An analogy is the difference between [[Scalar (mathematics)|scalar]] and vector arithmetic. A superscalar processor is a mixture of the two. Each instruction processes one data item, but there are multiple execution units within each CPU thus multiple instructions can be processing separate data items concurrently.

Superscalar CPU design emphasizes improving the instruction dispatcher accuracy and allowing it to keep the multiple execution units in use at all times. This has become increasingly important as the number of units has increased. While early superscalar CPUs would have two [[Arithmetic logic unit|ALU]]s and a single [[floating-point unit|FPU]], a later design such as the [[PowerPC 970]] includes four ALUs, two FPUs, and two SIMD units. If the dispatcher is ineffective at keeping all of these units fed with instructions, the performance of the system will be no better than that of a simpler, cheaper design.

A superscalar processor usually sustains an execution rate in excess of one [[Cycles per instruction|instruction per machine cycle]]. But merely processing multiple instructions concurrently does not make an architecture superscalar, since [[Instruction pipeline|pipelined]], [[multiprocessor]] or [[Multi-core (computing)|multi-core]] architectures also achieve that, but with different methods.

In a superscalar CPU the dispatcher reads instructions from memory and decides which ones can be run in parallel, dispatching each to one of the several execution units contained inside a single CPU. Therefore, a superscalar processor can be envisioned as having multiple parallel pipelines, each of which is processing instructions simultaneously from a single instruction thread.

Most modern superscalar CPUs also have logic to reorder the instructions to try to avoid pipeline stalls and increase parallel execution.