Editing System Management Bus (section)

===Electrical===
====Input Voltage (''V<sub>IL</sub>'' and ''V<sub>IH</sub>'')====
When mixing devices, the I²C specification defines the input levels to be 30% and 70% of the supply voltage ''V<sub>DD</sub>'',{{r|nxp_com_UM10204_3|p=9}} which may be 5&nbsp;V, 3.3&nbsp;V, or any other value. Instead of relating the bus input levels to ''V<sub>DD</sub>'', SMBus defines them to be fixed. SMBus 2.0 defines ''V<sub>IL,max</sub>'' at 0.8&nbsp;V and ''V<sub>IH,min</sub>'' at 2.1&nbsp;V, and supports a ''V<sub>DD</sub>'' ranging from 3 to 5&nbsp;V, while in SMBus 3.0, the levels are defined at 0.8 and 1.35&nbsp;V, with a ''V<sub>DD</sub>'' ranging from 1.8 to 5&nbsp;V.<ref name="smbus_org-smbus30" />

====Sink Current (''I<sub>OL</sub>'')====
SMBus 2.0 defines a ‘High Power’ class that includes a 4 mA sink current that cannot be driven by I²C chips unless the pull-up resistor is sized to I²C-bus levels.

NXP devices have a higher power set of electrical characteristics than SMBus 1.0. The main difference is the current sink capability with ''V<sub>OL</sub>'' = 0.4&nbsp;V.
*SMBus low power = 350 μA
*SMBus high power = 4 mA
*I²C-bus = 3 mA
SMBus ‘high power’ devices and I²C-bus devices will work together if the pull-up resistor is sized for 3&nbsp;mA.

====Frequency (''F<sub>MAX</sub>'' and ''F<sub>MIN</sub>'')====
The SMBus clock is defined from 10 to 100&nbsp;kHz while I²C can be 0–100&nbsp;kHz, 0–400&nbsp;kHz, 0–1&nbsp;MHz and 0–3.4&nbsp;MHz, depending on the mode. This means that an I²C bus running at less than 10&nbsp;kHz will not be SMBus compliant since the SMBus devices may time out. Many SMBus devices will however support lower frequencies.

SMBus 3.0 adds 400&nbsp;kHz and 1&nbsp;MHz bus speeds.

====Timing====
*SMBus defines a clock low time-out, TIMEOUT of 35&nbsp;ms. I²C does not specify any timeout limit.
*SMBus specifies T<sub>LOW:SEXT</sub> as the cumulative clock low extend time for a slave device. I²C does not have a similar specification.
*SMBus specifies T<sub>LOW:MEXT</sub> as the cumulative clock low extend time for a master device. Again I²C does not have a similar specification.
*SMBus defines both rise and fall time of bus signals. I²C does not.
*The SMBus time-out specifications do not preclude I²C devices co-operating reliably on the SMBus. It is the responsibility of the designer to ensure that I²C devices are not going to violate these bus timing parameters.