Editing System bus (section)

==Description==
To provide even more modularity with reduced cost, [[memory bus|memory]] and [[I/O bus]]es (and the required [[control bus|control]] and [[power bus]]es) were sometimes combined into a single unified system bus.<ref>{{cite book |title=The essentials of computer organization and architecture |author1=Linda Null |author2=Julia Lobur |publisher=Jones & Bartlett Learning |year=2010 |isbn= 978-1-4496-0006-8 |edition= 3rd |pages= 36,199–203 |url= https://books.google.com/books?id=f83XxoBC_8MC&pg=PA36 }}</ref>
Modularity and cost became important as computers became small enough to fit in a single cabinet (and customers expected similar price reductions).
[[Digital Equipment Corporation]] (DEC) further reduced cost for mass-produced [[minicomputer]]s, and [[memory-mapped I/O]] into the memory bus, so that the devices appeared to be memory locations.  This was implemented in the [[Unibus]] of the [[PDP-11]] around 1969, eliminating the need for a separate I/O bus.<ref>{{cite journal |title= A New Architecture for Mini-Computers—The DEC PDP-11 |author1= C. Gordon Bell |author2= R. Cady |author3= H. McFarland |author4= B. Delagi |author5= J. O'Laughlin |author6= R. Noonan |author7= W. Wulf |journal= Spring Joint Computer Conference |pages= 657–675 |year= 1970 |url= http://research.microsoft.com/en-us/um/people/gbell/CGB%20Files/New%20Architecture%20PDP11%20SJCC%201970%20c.pdf }}</ref>
Even computers such as the [[PDP-8]] without memory-mapped I/O were soon implemented with a system bus, which allowed modules to be plugged into any slot.<ref>{{cite book |title= Small Computer Handbook |publisher= Digital Equipment Corporation |year= 1973 |pages= 2–9<!-- not a range, chapter & page --> |url= http://www.bitsavers.org/pdf/dec/pdp8/handbooks/Small_Computer_Handbook_1973.pdf }}</ref>
Some authors called this a new streamlined "model" of  computer architecture.<ref>{{cite book |title= Computer architecture and organization: an integrated approach |author1= Miles J. Murdocca |author2= Vincent P. Heuring |page= 11 |publisher= John Wiley & Sons |year= 2007 |isbn= 978-0-471-73388-1 }}</ref>

Many early microcomputers (with a CPU generally on a single [[integrated circuit]]) were built with a single system bus, starting with the [[S-100 bus]] in the [[Altair 8800]] computer system in about 1975.<ref>{{cite web |title= Origins of S-100 computers |author= Herbert R. Johnson |url= http://retrotechnology.com/herbs_stuff/s_origins.html }}</ref>
The [[IBM PC]] used the [[Industry Standard Architecture]] (ISA) bus as its system bus in 1981. The passive backplanes of early models were replaced with the standard of putting the CPU and RAM on a [[motherboard]], with only optional [[daughterboard]]s or [[expansion card]]s in system bus slots.

[[Image:Shared memory.svg |thumb |upright=1.6 | Simple [[symmetric multiprocessing]] using a system bus ]]
The [[Multibus]] became a standard of the [[Institute of Electrical and Electronics Engineers]] as IEEE standard 796 in 1983.<ref>{{cite web |title= 796-1983 — IEEE Standard Microcomputer System Bus |publisher=  [[Institute of Electrical and Electronics Engineers]]  |year= 1983 |url= https://standards.ieee.org/ieee/796/1021/ |access-date= May 25, 2011 }}</ref> 
[[Sun Microsystems]] developed the [[SBus]] in 1989 to support smaller expansion cards.<ref>{{cite book |doi= 10.1109/CMPCON.1990.63672 |chapter= The SBus: Sun's high performance system bus for RISC workstations |title= Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage |pages= 189–194 |year= 1990 |last1= Frank |first1= E.H. |isbn= 0-8186-2028-5 |s2cid= 25815415 }}</ref>
The easiest way to implement [[symmetric multiprocessing]] was to plug in more than one CPU into the shared system bus, which was used through the 1980s.
However, the shared bus quickly became the bottleneck and more sophisticated connection techniques were explored.<ref>{{cite book |title= Bus and Cache Memory Organization for Multiprocessors |author= Donald Charles Winsor |year= 1989 |publisher= University of Michigan Electrical Engineering department |url= http://www.eecs.umich.edu/~tnm/trev_test/dissertationsPDF/donw.pdf |access-date= 2011-05-29 |archive-date= 2012-01-28 |archive-url= https://web.archive.org/web/20120128235658/http://www.eecs.umich.edu/~tnm/trev_test/dissertationsPDF/donw.pdf |url-status= dead }} Ph.D. dissertation.</ref>

Even in very simple systems, at various times the data bus is driven by the program memory, by RAM, and by I/O devices.
To prevent [[bus contention]] on the data bus, at any one instant only one device drives the data bus.
In very simple systems, only the data bus is required to be a bidirectional bus.
In very simple systems, the [[memory address register]] always drives the address bus, the [[control unit]] always drives the control bus,
and an [[address decoder]] selects which particular device is allowed to drive the data bus during this bus cycle.
In very simple systems, every [[instruction cycle]] starts with a READ memory cycle where program memory drives the instruction onto the data bus while the [[instruction register]] latches that instruction from the data bus.
Some instructions continue with a WRITE memory cycle where the [[memory data register]] drives data onto the data bus into the chosen RAM or I/O device.
Other instructions continue with another READ memory cycle where the chosen RAM, program memory, or I/O device drives data onto the data bus while the memory data register latches that data from the data bus.

More complex systems have a [[multi-master bus]]—not only do they have many devices that each drive the data bus, but also have many [[bus master]]s that each drive the address bus.
The address bus as well as the data bus in [[bus snooping]] systems is required to be a bidirectional bus, often implemented as a [[three-state bus]].
To prevent bus contention on the address bus, a [[bus arbiter]] selects which particular bus master is allowed to drive the address bus during this bus cycle.