Editing Systolic array (section)

==Architecture==
A systolic array typically consists of a large [[monolithic system|monolithic]] [[Graph (discrete mathematics)|network]] of primitive computing [[Node (computer science)|node]]s which can be hardwired or software configured for a specific application. The nodes are usually fixed and identical, while the interconnect is programmable. The more general '''wavefront''' processors, by contrast, employ sophisticated and individually programmable nodes which may or may not be monolithic, depending on the array size and design parameters. The other distinction is that systolic arrays rely on [[synchronous]] data transfers, while [[wavefront]] tend to work [[wikt:asynchronous|asynchronous]]ly.

Unlike the more common [[Von Neumann architecture]], where program execution follows a script of instructions stored in common memory, [[address space|addressed]] and sequenced under the control of the [[CPU]]'s [[program counter]] (PC), the individual nodes within a systolic array are triggered by the arrival of new data and always process the data in exactly the same way. The actual processing within each node may be hard wired or block [[microcode|micro code]]d, in which case the common node personality can be block programmable.

The systolic array paradigm with data-streams driven by data [[Counter (digital)|counter]]s, is the counterpart of the Von Neumann architecture with instruction-stream driven by a program counter. Because a systolic array usually sends and receives multiple data streams, and multiple data counters are needed to generate these data streams, it supports [[data parallelism]].