Editing Test-and-set (section)

=== Variation 1 ===
When CPU 1 issues a test-and-set instruction, the DPRAM first makes an "internal note" of this by storing the address of the memory location in a special place.  If at this point, CPU 2 happens to issue a test-and-set instruction for the same memory location, the DPRAM first checks its "internal note", recognizes the situation, and issues a BUSY interrupt, which tells CPU 2 that it must wait and retry.  This is an implementation of a [[busy waiting]] or [[spinlock]] using the interrupt mechanism.  Since all this happens at hardware speeds, CPU 2's wait to get out of the spin-lock is very short.

Whether or not CPU 2 was trying to access the memory location, the DPRAM performs the test given by CPU 1.  If the test succeeds, the DPRAM sets the memory location to the value given by CPU 1.  Then the DPRAM wipes out its "internal note" that CPU 1 was writing there.  At this point, CPU 2 could issue a test-and-set, which would succeed.