Editing Transistor–transistor logic (section)

== Implementation ==

=== Fundamental TTL gate ===
[[File:TTL npn nand.svg|thumb|Two-input TTL [[NAND gate]] with a simple output stage (simplified)]]

TTL inputs are the emitters of bipolar transistors. In the case of NAND inputs, the inputs are the emitters of [[multiple-emitter transistor]]s, functionally equivalent to multiple transistors where the bases and collectors are tied together.<ref>{{citation |title=Electronic Principles Physics, Models, and Circuits |edition=1st |year=1969 |last1=Gray |first1=Paul E. |last2=Searle |first2=Campbell L. |publisher=Wiley |isbn=978-0471323983 |page=870}}</ref> The transistor's collector is buffered by a [[common emitter]] amplifier.

'''Inputs both logical ones.''' When all the inputs are held at high voltage, the base–emitter junctions of the multiple-emitter transistor are reverse-biased. Unlike DTL, a small collector current (approximately 10 μA) is drawn by each of the inputs. This is because the transistor is in [[Bipolar junction transistor#Regions of operation|reverse-active mode]]. An approximately constant current flows from the positive rail, through the resistor and into the base of the multiple emitter transistor.<ref>{{harvnb|Buie|1966|loc=column 4}}</ref> This current passes through the base–emitter junction of the output transistor, allowing it to conduct and pulling the output voltage low (logical zero).

'''An input logical zero.''' Note that the base–collector junction of the multiple-emitter transistor and the base–emitter junction of the output transistor are in series between the bottom of the resistor and ground. If one input voltage becomes zero, the corresponding base–emitter junction of the multiple-emitter transistor is in parallel with these two junctions. A phenomenon called current steering means that when two voltage-stable elements with different threshold voltages are connected in parallel, the current flows through the path with the smaller threshold voltage. That is, current flows out of this input and into the zero (low) voltage source. As a result, no current flows through the base of the output transistor, causing it to stop conducting and the output voltage becomes high (logical one). During the transition the input transistor is briefly in its active region; so it draws a large current away from the base of the output transistor and thus quickly discharges its base. This is a critical advantage of TTL over DTL that speeds up the transition over a diode input structure.<ref>{{citation |last=Millman |first=J. |title=Microelectronics: Digital and Analog Circuits and Systems |location=New York |publisher=McGraw-Hill Book Company |year=1979 |isbn=0-07-042327-X |page=[https://archive.org/details/microelectronics0000mill/page/147 147] |url=https://archive.org/details/microelectronics0000mill }}</ref>

The main disadvantage of TTL with a simple output stage is the relatively high output resistance at output [[Logic level|logical "1"]] that is completely determined by the output collector resistor. It limits the number of inputs that can be connected (the [[fanout]]). Some advantage of the simple output stage is the high voltage level (up to V<sub>CC</sub>) of the output logical "1" when the output is not loaded.

=== Open collector wired logic ===
{{Main articles|Wired logic connection|Open collector}}
A common variation omits the collector resistor of the output transistor, making an [[open-collector]] output. This allows the designer to fabricate [[Wired logic connection|wired logic]] by connecting the open-collector outputs of several logic gates together and providing a single external [[pull-up resistor]]. If any of the logic gates becomes logic low (transistor conducting), the combined output will be low. Examples of this type of gate are the 7401<ref>[https://www.ti.com/lit/ds/symlink/sn5401.pdf Quadruple 2-Input Positive-NAND Gates With Open-Collector Outputs]</ref> and 7403<ref>[https://www.ti.com/lit/ds/symlink/sn74ls03.pdf Quadruple 2-Input Positive-NAND Gates With Open-Collector Outputs] </ref> series. Open-collector outputs of some gates have a higher maximum voltage, such as 15 V for the 7426,<ref>[https://www.ti.com/lit/ds/symlink/sn54ls26.pdf Quadruple 2-Input High-Voltage Interface Positive-NAND Gates ]</ref> useful when driving non-TTL loads.

=== TTL with a "totem-pole" output stage ===
[[File:7400 Circuit.svg|thumb|Standard TTL NAND with a "totem-pole" output stage, one of four in 7400]]

To solve the problem with the high output resistance of the simple output stage the second schematic adds to this a "totem-pole" ("[[push–pull output|push–pull]]") output. It consists of the two n-p-n transistors V<sub>3</sub> and V<sub>4</sub>, the "lifting" diode V<sub>5</sub> and the current-limiting resistor R<sub>3</sub> (see the figure on the right). It is driven by applying the same ''current steering'' idea as above.

When V<sub>2</sub> is "off", V<sub>4</sub> is "off" as well and V<sub>3</sub> operates in active region as a [[Common collector|voltage follower]] producing high output voltage (logical "1").

When V<sub>2</sub> is "on", it activates V<sub>4</sub>, driving low voltage (logical "0") to the output. Again there is a current-steering effect: the series combination of V<sub>2</sub>'s C-E junction and V<sub>4</sub>'s B-E junction is in parallel with the series of V<sub>3</sub> B-E, V<sub>5</sub>'s anode-cathode junction, and V<sub>4</sub> C-E. The second series combination has the higher threshold voltage, so no current flows through it, i.e. V<sub>3</sub> base current is deprived. Transistor V<sub>3</sub> turns "off" and it does not impact on the output.

In the middle of the transition, the resistor R<sub>3</sub> limits the current flowing directly through the series connected transistor V<sub>3</sub>, diode V<sub>5</sub> and transistor V<sub>4</sub> that are all conducting. It also limits the output current in the case of output logical "1" and short connection to the ground. The strength of the gate may be increased without proportionally affecting the power consumption by removing the pull-up and pull-down resistors from the output stage.<ref>[http://www.siliconfareast.com/ttl.htm ''Transistor–Transistor Logic (TTL).''] siliconfareast.com. 2005. Retrieved 17 September 2008. p. 1.</ref><ref>Tala, D. K. [http://www.asic-world.com/digital/gates5.html ''Digital Logic Gates Part-V.''] asic-world.com. 2006.</ref>

The main advantage of TTL with a "totem-pole" output stage is the low output resistance at output logical "1". It is determined by the upper output transistor V<sub>3</sub> operating in active region as an [[emitter follower]]. The resistor R<sub>3</sub> does not increase the output resistance since it is connected in the V<sub>3</sub> collector and its influence is compensated by the negative feedback. A disadvantage of the "totem-pole" output stage is the decreased voltage level (no more than 3.5 V) of the output logical "1" (even if the output is unloaded). The reasons for this reduction are the voltage drops across the V<sub>3</sub> base–emitter and V<sub>5</sub> anode–cathode junctions.