Editing Translation lookaside buffer (section)

==Performance implications==
[[File:Steps In a Translation Lookaside Buffer.png|thumb|361x361px|Flowchart<ref>{{Cite book|title=Operating Systems: Internals and Design Principles|last=Stallings|first=William|publisher=Pearson|year=2014|isbn=978-0133805918|location=United States of America}}</ref> shows the working of a translation lookaside buffer. For simplicity, the page-fault routine is not mentioned.]]
The CPU has to access main memory for an instruction-cache miss, data-cache miss, or TLB miss.  The third case (the simplest one) is where the desired information itself actually ''is'' in a cache, but the information for virtual-to-physical translation is not in a TLB. These are all slow, due to the need to access a slower level of the memory hierarchy, so a well-functioning TLB is important. Indeed, a TLB miss can be more expensive than an instruction or data cache miss, due to the need for not just a load from main memory, but a page walk, requiring several memory accesses.

The flowchart provided explains the working of a TLB. If it is a TLB miss, then the CPU checks the page table for the page table entry. If the ''present bit'' is set, then the page is in main memory, and the processor can retrieve the frame number from the page-table entry to form the physical address.<ref>{{Cite book|title=Fundamentals of Parallel Multicore Architecture|last=Solihin|first=Yan|publisher=Taylor & Francis Group|year=2016|isbn=978-0-9841630-0-7|location=Boca Raton, FL}}</ref> The processor also updates the TLB to include the new page-table entry. Finally, if the present bit is not set, then the desired page is not in the main memory, and a [[page fault]] is issued. Then a page-fault interrupt is called, which executes the page-fault handling routine.

If the page [[working set]] does not fit into the TLB, then [[TLB thrashing]] occurs, where frequent TLB misses occur, with each newly cached page displacing one that will soon be used again, degrading performance in exactly the same way as thrashing of the instruction or data cache does. TLB thrashing can occur even if instruction-cache or data-cache [[thrashing (computer science)|thrashing]] are not occurring, because these are cached in different-size units. Instructions and data are cached in small blocks ([[cache line]]s), not entire pages, but address lookup is done at the page level. Thus, even if the code and data working sets fit into cache, if the working sets are fragmented across many pages, the virtual-address working set may not fit into TLB, causing TLB thrashing. Appropriate sizing of the TLB thus requires considering not only the size of the corresponding instruction and data caches, but also how these are fragmented across multiple pages.