Editing Turbo code (section)

==An example encoder==
There are many different instances of turbo codes, using different component encoders, input/output ratios, interleavers, and [[Punctured code|puncturing patterns]].  This example encoder implementation describes a classic turbo encoder, and demonstrates the general design of parallel turbo codes.

This encoder implementation sends three sub-blocks of bits.  The first sub-block is the ''m''-bit block of payload data.  The second sub-block is ''n/2'' parity bits for the payload data, computed using a recursive systematic [[convolutional code]] (RSC code).  The third sub-block is ''n/2'' parity bits for a known [[permutation]] of the payload data, again computed using an RSC code.  Thus, two redundant but different sub-blocks of parity bits are sent with the payload. The complete block has {{nowrap|''m'' + ''n''}} bits of data with a code rate of {{nowrap|''m''/(''m'' + ''n'')}}. The [[permutation]] of the payload data is carried out by a device called an [[interleaver]].

Hardware-wise, this turbo code encoder consists of two identical RSC coders, ''C''<sub>1</sub> and ''C''<sub>2</sub>, as depicted in the figure, which are connected to each other using a concatenation scheme, called ''parallel concatenation'':

[[File:turbo encoder.svg]]

In the figure, ''M'' is a memory register. The delay line and interleaver force input bits d<sub>k</sub> to appear in different sequences.
At first iteration, the input sequence ''d''<sub>k</sub> appears at both outputs of the encoder, ''x''<sub>k</sub> and'' y''<sub>1k</sub> or ''y''<sub>2k</sub> due to the encoder's systematic nature. If the encoders ''C''<sub>1</sub> and ''C''<sub>2</sub> are used in ''n''<sub>1</sub> and ''n''<sub>2</sub> iterations, their rates are respectively equal to

:<math>\begin{align}
  ~R_1 &= \frac{n_1 + n_2}{2n_1 + n_2}\\
  ~R_2 &= \frac{n_1 + n_2}{n_1 + 2n_2}
\end{align}</math>