Editing Unibus (section)

==Pinout==
{| class="wikitable"
!Number!!Name!!Type!!Description
|-
|18||A00-A17 || 1 || Address Lines
|-
|16||D00-D15 || 1 || Data Lines
|-
| 4||BR4-BR7 || 1 || Bus (Interrupt) Requests at priorities 4 (lowest) through 7 (highest)
|-
| 4||BG4-BG7 || 2 || Bus (Interrupt) Grants at priorities 4 (lowest) through 7 (highest)
|-
| 1||NPR     || 1 || Non Processor (DMA) Request
|-
| 1||NPG     || 2 || Non Processor (DMA) Grant
|-
| 1||MSYNC   || 1 || Master Sync
|-
| 1||SSYNC   || 1 || Slave Sync
|-
| 1||BBSY    || 1 || Bus Busy
|-
| 1||SACK    || 1 || Selection Acknowledge
|-
| 1||INIT    || 1 || Bus Init
|-
| 1||INTR    || 1 || Interrupt Request
|-
| 1||PA      || 1 || Parity control
|-
| 1||PB      || 1 || Parity control
|-
| 2||C0-C1   || 1 || Control Lines
|-
| 1||ACLO    || 3 || AC Low
|-
| 1||DCLO    || 3 || DC Low
|-
| 2||+5v     || - || Power Lines (not counted as part of the 56)
|-
|14||Gnd     || - || Ground Lines (not counted as part of the 56)
|}

[[File:Unibus grant continuity card.jpg|thumb|Unibus grant request continuity card]]
Type 1 lines are a normal multi-sender [[wired logic connection|wired-OR]] bus with [[pull-up resistor]]s at each end of the bus, typically on a [[electrical termination|terminator]] card.<ref name=specification/>

Type 2 lines are selectively propagated by each card to the next slot – if the card wants to keep the request grant it will assert the SACK line and not propagate the request to the next slot. If a slot is empty, it is necessary to install a "grant continuity card" in the slot to propagate the four type 2 signals to the next card.<ref name=specification/>

Type 3 signals are generated by the power supply and have only a single sender. They warn the devices on the bus when the power is about to fail, so those devices can execute an orderly shutdown, and disable operations to prevent spurious writes.<ref name=specification>{{cite web |url= http://www.bitsavers.org/pdf/dec/unibus/UnibusSpec1979.pdf |title= Unibus Specification |date= 1979 |author= Digital Equipment Corporation}}</ref>

The two control lines (C0 and C1) allowed the selection of four different data transfer cycles:
*DATI (Data In, a read)
*DATIP (Data In/Pause, the first portion of a Read-Modify-Write operation. A DATO or DATOB operation completes this.)
*DATO (Data Out, a word write)
*DATOB (Data Out/Byte, a byte write)
*During an interrupt cycle, a fifth style of transfer was automatically invoked to convey an ''interrupt vector'' from the interrupting device to the ''interrupt-fielding processor''.