Editing Universal asynchronous receiver-transmitter (section)

==Transmitting and receiving serial data==
{{See also |Asynchronous serial communication}}
A UART contains those following components:

* a clock generator, usually a multiple of the bit rate to allow sampling in the middle of a bit period
* input and output shift registers, along with the transmit/receive or FIFO buffers
* transmit/receive control
* read/write control logic

The universal asynchronous receiver-transmitter (UART) takes bytes of data and transmits the individual bits in a sequential fashion.<ref name=Osborne80>Adam Osborne, ''An Introduction to Microcomputers Volume 1: Basic Concepts'', Osborne-McGraw Hill Berkeley California USA, 1980 {{ISBN|0-931988-34-9}} pp. 116–126</ref> At the destination, a second UART re-assembles the bits into complete bytes. Each UART contains a [[shift register]], which is the fundamental method of conversion between serial and parallel forms. Serial transmission of digital information (bits) through a single wire or other medium is less costly than parallel transmission through multiple wires.

The UART usually does not directly generate or receive the external signals used between different items of equipment. Separate interface devices are used to convert the [[logic level]] signals of the UART to and from the external signaling levels, which may be standardized voltage levels, current levels, or other signals.

Communication may be 3 modes:
* ''[[Simplex communication|simplex]]'' (in one direction only, with no provision for the receiving device to send information back to the transmitting device)
* ''[[Duplex (telecommunications)#Full_duplex|full duplex]]'' (both devices send and receive at the same time)
* ''[[Duplex (telecommunications)#Half_duplex|half duplex]]'' (devices take turns transmitting and receiving)

For UART to work the following settings need to be the same on both the transmitting and receiving side:

* Voltage level
* [[Baud Rate]]
* [[Parity bit]] 
* Data bits size
* Stop bits size 
* [[Flow control (data)|Flow Control]]

For the voltage level, two UART modules work well when they both have the same voltage level, e.g 3V-3V between the two UART modules. To use two UART modules at different voltage levels, a level shifting circuit needs to be added externally.<ref name="Low Voltage Translation for SPI, UART, RGMII, JTAG Interfaces (Rev. B)
">{{cite web |author1= Texas Instrument |title=Universal asynchronous receiver/transmitter (UART) |url=https://www.ti.com/lit/an/scea065b/scea065b.pdf?ts=1692931646648|website=ti.com|access-date=25 Aug 2023 |page=6, "2.3.1 Voltage Translation With UART"|language=en |format=PDF |date=2021-03-01 }}</ref>

=== Data framing ===
[[File:UART-signal.png|class=skin-invert-image|thumb|400px|right|Example of a UART frame. In this diagram, one [[byte]] is sent, consisting of a start bit, followed by eight data bits (D1-8), and two stop bits, for a 11-bit UART frame. The number of data and formatting bits, the presence or absence of a parity bit, the form of parity (even or odd) and the transmission speed must be pre-agreed by the communicating parties. The "stop bit" is actually a "stop period"; the stop period of the transmitter may be arbitrarily long. It cannot be shorter than a specified amount, usually 1 to 2 bit times. The receiver requires a shorter stop period than the transmitter. At the end of each data frame, the receiver stops briefly to wait for the next start bit. It is this difference that keeps the transmitter and receiver synchronized.
BCLK = Base Clock]]

A UART frame consists of five elements:

* Idle (logic high (1)) 
* Start bit (logic low (0)): the start bit signals to the receiver that a new character is coming.
* Data bits: the next five to nine bits, depending on the code set employed, represent the character.
* Parity bit: if a parity bit is used, it would be placed after all of the data bits. The parity bit is a way for the receiving UART to tell if any data has changed during transmission.
* Stop (logic high (1)): the next one or two bits are always in the '''mark''' (logic high, i.e., 1) condition and called the stop bit(s). They signal to the receiver that the character is complete. Since the start bit is logic low (0) and the stop bit is logic high (1) there are always at least two guaranteed signal changes between characters. If the line is held in the logic low condition for longer than a character time, this is a '''break''' condition that can be detected by the UART.

In the most common settings of 8 data bits, no parity and 1 stop bit (i.e. [[8N1]]), the protocol efficiency is 8/10 = 80%. For comparison, [[Ethernet frame|Ethernet]]'s protocol efficiency when using [[Ethernet frame#Maximum throughput|maximum throughput frames]] with payload of 1500 bytes is up to 95% and up to 99% with 9000 byte [[jumbo frame]]s. However due to Ethernet's [[protocol overhead]] and minimum payload size of 42 bytes, if small messages of one or a few bytes are to be sent, Ethernet's protocol efficiency drops much lower than the UART's 8N1 constant efficiency of 80%.

The idle, no data state is high-voltage, or powered. This is a historic legacy from telegraphy, in which the line is held high to show that the line and transmitter are not damaged.

Each character is framed as a logic low start bit, data bits, possibly a [[parity bit]] and one or more stop bits. In most applications, the least significant data bit (the one on the left in this diagram) is transmitted first, but there are exceptions (such as the [[IBM 2741]] printing terminal).

===Receiver===
All operations of the UART hardware are controlled by an internal clock signal which runs at a multiple of the data rate, typically 8 or 16 times the bit rate. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, it is considered a spurious pulse and is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register are made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processor [[interrupt]] to request that the host processor transfers the received data.

Communicating UARTs have no shared timing system apart from the communication signal. Typically, UARTs resynchronize their internal clocks on each change of the data line that is not considered a spurious pulse. Obtaining timing information in this manner, they reliably receive when the transmitter is sending at a slightly different speed than it should. Simplistic UARTs do not do this; instead they resynchronize on the falling edge of the start bit only, and then read the center of each expected data bit, and this system works if the broadcast data rate is accurate enough to allow the stop bits to be sampled reliably.<ref name="AN2141">{{cite web |title=Determining Clock Accuracy Requirements for UART Communications |url=https://pdfserv.maximintegrated.com/en/an/AN2141.pdf |website=an2141 |publisher=[[Maxim Integrated]] |access-date=1 November 2021 |language=EN |date=2003-08-07}}</ref><ref name="nxp_SCC2691">{{cite web |author1= |title=Universal asynchronous receiver/transmitter (UART) |url=https://www.nxp.com/docs/en/data-sheet/SCC2691.pdf#page=14 |website=SCC2691 |publisher=Philips [[NXP]] |access-date=1 November 2021 |page=14 |language=en |format=PDF |date=2006-08-04 }}</ref>

It is a standard feature for a UART to store the most recent character while receiving the next. This "double buffering" gives a receiving computer an entire character transmission time to fetch a received character. Many UARTs have a small first-in, first-out ([[FIFO (computing and electronics)|FIFO]]) buffer memory between the receiver shift register and the host system interface. This allows the host processor even more time to handle an interrupt from the UART and prevents loss of received data at high rates.

===Transmitter===
Transmission operation is simpler as the timing does not have to be determined from the line state, nor is it bound to any fixed timing intervals. As soon as the sending system deposits a character in the shift register (after completion of the previous character), the UART generates a start bit, shifts the required number of data bits out to the line, generates and sends the parity bit (if used), and sends the stop bits. Since full-duplex operation requires characters to be sent and received at the same time, UARTs use two different shift registers for transmitted and received characters. High performance UARTs could contain a transmit FIFO (first in first out) buffer to allow a [[CPU]] or DMA controller to deposit multiple characters in a burst into the FIFO rather than have to deposit one character at a time into the shift register. Since transmission of a single or multiple characters may take a long time relative to CPU speeds, a UART maintains a flag showing busy status so that the host system knows if there is at least one character in the transmit buffer or shift register; "ready for next character(s)" may also be signaled with an interrupt.

===Application===
Transmitting and receiving UARTs must be set for the same bit speed (Baud rate), character length, parity, and number of stop bits for proper operation. The receiving UART may detect some mismatched settings and set a "framing error" flag bit for the host system; in exceptional cases, the receiving UART will produce an erratic stream of mutilated characters and transfer them to the host system.

Typical serial ports used with personal computers connected to modems use one start bit, eight data bits, no parity, and one stop bit; for this configuration, the number of ASCII characters per second equals the bit rate divided by 10.

Some very low-cost [[home computers]] or [[embedded systems]] that lack a physical UART may instead [[Emulator|emulate]] the protocol with software by sampling the state of an input port or directly manipulating an output port for data transmission. While very CPU-intensive (since the CPU timing is critical), the UART chip can thus be omitted, saving money and space. The technique is known as [[bit-banging]].