Editing Verilog (section)

==History==

===Beginning===
Verilog was created by [[Prabhu Goel]], [[Phil Moorby]] and Chi-Lai Huang between late 1983 and early 1984.<ref>{{cite magazine |title=Verilog's inventor nabs EDA's Kaufman award |date= 7 November 2005 |magazine=EE Times |url=http://www.eetimes.com/document.asp?doc_id=1157349}}</ref> Chi-Lai Huang had earlier worked on a hardware description LALSD, a language developed by Professor [[S.Y.H. Su]], for his PhD work.<ref>{{cite book |first1=Chi-Lai |last1=Huang |first2=S.Y.H. |last2=Su |chapter=Approaches for Computer-Aided Logic System Design Using Hardware Description Language |title=Proceedings of International Computer Symposium 1980, Taipei, Taiwan, December 1980 |pages=772–79O |oclc=696254754}}</ref> The rights holder for this process, at the time proprietary, was "Automated Integrated Design Systems" (later renamed to [[Gateway Design Automation]] in 1985). Gateway Design Automation was purchased by [[Cadence Design Systems]] in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de facto standard (of Verilog [[logic simulator]]s) for the next decade. Originally, Verilog was only intended to describe and allow simulation; the automated synthesis of subsets of the language to physically realizable structures (gates etc.) was developed after the language had achieved widespread usage.

Verilog is a portmanteau of the words "verification" and "logic".<ref>{{cite web |title=Oral History of Philip Raymond "Phil" Moorby |date=22 April 2013 |publisher=Computer History Museum |url=http://archive.computerhistory.org/resources/access/text/2013/11/102746653-05-01-acc.pdf |pages=23–25}}</ref>

===Verilog-95===
With the increasing success of [[VHDL]] at the time, Cadence decided to make the language available for open [[standardization]]. Cadence transferred Verilog into the public domain under the [http://www.ovi.org/ Open Verilog International] (OVI) (now known as [[Accellera]]) organization. Verilog was later submitted to [[IEEE]] and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.

In the same time frame Cadence initiated the creation of [[Verilog-A]] to put standards support behind its analog simulator [[Spectre Circuit Simulator|Spectre]]. Verilog-A was never intended to be a standalone language and is a subset of [[Verilog-AMS]] which encompassed Verilog-95.

===Verilog 2001===
Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became [[IEEE]] Standard 1364-2001 known as Verilog-2001.

Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2's complement) signed nets and variables. Previously, code authors had to perform signed operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8-bit addition required an explicit description of the Boolean algebra to determine its correct value). The same function under Verilog-2001 can be more succinctly described by one of the built-in operators: +, -, /, *, >>>. A generate–endgenerate construct (similar to VHDL's generate–endgenerate) allows Verilog-2001 to control instance and statement instantiation through normal decision operators (case–if–else). Using generate–endgenerate, Verilog-2001 can instantiate an array of instances, with control over the connectivity of the individual instances. File I/O has been improved by several new system tasks. And finally, a few syntax additions were introduced to improve code readability (e.g. always @*, named parameter override, C-style function/task/module header declaration).

Verilog-2001 is the version of Verilog supported by the majority of commercial [[Electronic design automation|EDA]] software packages.

===Verilog 2005===
Not to be confused with [[SystemVerilog]], ''Verilog 2005'' ([[IEEE]] Standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword).

A separate part of the Verilog standard, [[Verilog-AMS]], attempts to integrate analog and mixed signal modeling with traditional Verilog.

===SystemVerilog===
{{Main|SystemVerilog}}
The advent of [[hardware verification language]]s such as OpenVera, and Verisity's [[e (verification language)|e language]] encouraged the development of [[Superlog HDL|Superlog]] by Co-Design Automation Inc (acquired by [[Synopsys]]). The foundations of Superlog and Vera were donated to [[Accellera]], which later became the IEEE standard P1800-2005: SystemVerilog.

SystemVerilog is a [[superset]] of Verilog-2005, with many new features and capabilities to aid design verification and design modeling. As of 2009, the SystemVerilog and Verilog language standards were merged into SystemVerilog 2009 (IEEE Standard 1800-2009).

===Updates since 2009===

The SystemVerilog standard was subsequently updated in 2012,<ref>[https://standards.ieee.org/ieee/1800/4934/ IEEE 1800-2012], [[IEEE]], 2012</ref> 2017,<ref>[https://standards.ieee.org/ieee/1800/6700/ IEEE 1800-2017], [[IEEE]], 2017</ref> and most recently in December 2023.<ref name="IEEE2023">[https://standards.ieee.org/ieee/1800/7743/ IEEE 1800-2023, IEEE Approved Draft Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language], [[IEEE]], 2023</ref>