Editing Wafer testing (section)

==Testing==
When all test patterns pass for a specific die, its position is remembered for later use during [[integrated circuit packaging|IC packaging]]. Historically, non-passing circuits were marked with a small dot of ink in the middle of the die, today this information is stored in a file, named a wafermap. This wafermap is then sent to the [[die attachment]] process which then only selects good dies.  When ink dots were used, vision systems on subsequent die handling equipment recognized the ink dot.  For today's multi-die packages such as stacked [[chip-scale package]] (SCSP) or system in package  (SiP) – the development of non-contact (RF) probes for identification of known tested die (KTD) and known good die (KGD) are critical to increasing overall system yield.

In some specific cases, a chip that passes some but not all tests can still be used as a product with limited functionality. The most common example of this is a memory chip for which only one part of the memory is functional. In this case, the chip can sometimes still be sold as a lower cost part with a smaller amount of memory.  In other specific cases, a defective chip may be repaired (e.g. by laser repair) using redundant spare circuitry. 

After IC packaging, a packaged chip will be tested again during the [[Semiconductor fabrication#Device test|IC testing]] phase, usually with the same or very similar tests and tester as for WFT. For this reason, it may be thought that WFT is an unnecessary, redundant step. This is not usually the case, since the removal of defective dies saves the considerable cost of packaging faulty devices. However, when WFT yield is so high that wafer testing is more expensive than the packaging cost of defect devices, the wafer testing step can be skipped altogether and chips undergo blind assembly.