Editing Watchdog timer (section)

==Architecture and operation==

===Restarting===
[[File:WatchdogWindow.png|thumb|300px|Some watchdog timers only allow kicks during a time window. Kicks occurring outside the window have no effect on the timer and may be treated as faults.]]
The act of restarting a watchdog timer is commonly referred to as ''kicking''{{efn|name=fn1|Various terms are used for the act of restarting a watchdog timer. Some (e.g. ''kick'', ''pet'', ''feed'', ''tickle'') draw a connection to [[guard dog]]s, whereas others (e.g. ''tag'', ''ping'', ''reset'') do not. This article uses ''kick'' for consistency.}} the watchdog.<ref name="ESD"/><ref name="SMSWT"/> In electronic watchdogs, kicking is typically done by writing to a watchdog control [[Memory-mapped I/O|port]] or by setting a particular bit in a [[hardware register|register]]. Alternatively, some tightly coupled{{efn|A ''tightly coupled'' watchdog timer is effectively a built-in extension of the processor and, as such, may be accessed by special [[machine language]] instructions which are specific to it.}} watchdog timers are kicked by executing a special [[machine language]] instruction. An example of this is the CLRWDT (clear watchdog timer) instruction found in the instruction set of some [[PIC microcontroller]]s.

In computers that are running [[operating system]]s, electronic watchdog restarts are usually invoked through a [[device driver]]. For example, in the [[Linux operating system]], a [[user space]] program will kick the watchdog by interacting with the watchdog device driver, typically by writing a zero character to {{mono|/dev/watchdog}} or by calling a KEEPALIVE [[ioctl]].<ref name="LinuxWatchdogApi"/> The device driver, which serves to abstract the watchdog hardware from user space programs, may also be used to configure the time-out period and start and stop the timer.

Some watchdog timers will only allow kicks during a specific time window. The window timing is usually relative to the previous kick or, if the watchdog has not yet been kicked, to the moment the watchdog was enabled. The window begins after a delay following the previous kick, and ends after a further delay. If the computer attempts to kick the watchdog before or after the window, the watchdog will not be restarted, and in some implementations this will be treated as a fault and trigger corrective action.<ref name="oracle"/>

===Enabling===
A watchdog timer is said to be ''enabled'' when operating and ''disabled'' when idle. Upon power-up, a watchdog may be unconditionally enabled or it may be initially disabled and require an external signal to enable it. In the latter case, the enabling signal may be automatically generated by hardware or it may be generated under software control.

<gallery class="center" mode="nolines" heights="220" widths="280" Caption="Watchdog state diagrams">
File:Watchdog timer state diagram with autostart.svg|Unconditionally enabled watchdog
File:Watchdog timer state diagram with enable.svg|Watchdog with ''enable'' input signal
</gallery>

When automatically generated, the enabling signal is typically derived from the computer reset signal. In some systems the reset signal is directly used to enable the watchdog. In others, the reset signal is delayed so that the watchdog will become enabled at some later time following the reset. This delay allows time for the computer to boot before the watchdog is enabled. Without this delay, the watchdog would timeout and invoke a subsequent reset before the computer can run its application software — the software which kicks the watchdog — and the system would become stuck in an endless cycle of incomplete reboots.

===Single-stage watchdog===
Watchdog timers come in many configurations, and many allow their configurations to be altered. For example, the watchdog and CPU may share a common [[clock signal]] as shown in the block diagram below, or they may have independent clock signals or in some cases the watchdog may have no clock signal at all. A basic watchdog timer has a single timer which, upon timeout, typically will reset the CPU:

[[File:SimpleWatchdogTimer.gif|300px|center|alt=Block diagram of a simple, single-stage watchdog timer. The common clock is characteristic of basic watchdog microcontrollers.]]

===Multistage watchdog===
Two or more timers are sometimes cascaded to form a ''multistage watchdog timer'', where each timer is referred to as a ''timer stage'', or simply a ''stage''. For example, the block diagram below shows a three-stage watchdog. Depending on the design, this may be implemented with multiple timers, or by emulating multiple timers with a single timer and additional logic.

In a multistage watchdog, only the first stage is kicked by the processor. Upon first stage timeout, a corrective action is initiated and the next stage in the cascade is started. As each subsequent stage times out, it triggers a corrective action and starts the next stage. Upon final stage timeout, a corrective action is initiated, but no other stage is started because the end of the cascade has been reached. Typically, single-stage watchdog timers are used to simply restart the computer, whereas multistage watchdog timers will sequentially trigger a series of corrective actions, with the final stage triggering a computer restart.<ref name=SMSWT/>

[[File:Watchdog3stage.gif|550px|center|alt=A three-stage electronic watchdog timer.]]

===Time intervals===
Watchdog timers may have either fixed or programmable time intervals. Some watchdog timers allow the time interval to be programmed by selecting from among a few selectable, discrete values. In others, the interval can be programmed to arbitrary values. Typically, watchdog time intervals range from ten milliseconds to a minute or more. In a multistage watchdog, each timer may have its own, unique time interval.