Editing X86 (section)

==Chronology==
{{More citations needed section|date=March 2020}}
The table below lists processor models and model series implementing various architectures in the x86 family, in chronological order. Each line item is characterized by significantly improved or commercially successful processor microarchitecture designs.
{{mw-datatable}}
{| class="wikitable mw-datatable" style="text-align:center"
|+Chronology of x86 processors
|-
! colspan="2" rowspan="2"|Era
! rowspan="2" |Introduction
! rowspan="2" |Prominent CPU models
! colspan="3" |[[Address space]]
! rowspan="2" |Notable features
|-
![[Linear address space|Linear]]
![[Virtual address space|Virtual]]
![[Physical address|Physical]]
|-
| rowspan="3" style="vertical-align: middle; font-size: smaller;"|x86-16 ||rowspan="2" style="width:80px"|'''1st''' || 1978 || [[Intel 8086]], [[Intel 8088]] (1979) || rowspan="3" style="background: #FAECC8;" |16-bit ||rowspan="2" style="background: #FAECC8;" |NA ||rowspan="2" style="background: #FAECC8;" |20-bit || [[16-bit computing|16-bit]] [[instruction set architecture|ISA]], [[IBM PC]] (8088), [[IBM PC/XT]] (8088)
|-
| rowspan="2" |1982 || [[Intel 80186]], [[Intel 80188]]<br/>[[NEC V20]]/V30 (1983) || 8086-2 ISA, embedded (80186/80188)
|-
| '''2nd''' || [[Intel 80286]] and clones || style="background: #FAECC8;" |30-bit ||style="background: #FAECC8;" |24-bit || [[protected mode]], [[IBM Personal Computer XT|IBM PC/XT 286]], [[IBM Personal Computer/AT|IBM PC/AT]]
|-
| rowspan="13" style="vertical-align: middle; font-size: smaller;" |[[IA-32]] ||rowspan="1" style="width:80px"|'''3rd''' || 1985 || [[Intel 80386]], [[AMD Am386]] (1991) || rowspan="13" style="background: #CEE0F2;" |32-bit || rowspan="13" style="background: #CEE0F2;" |46-bit ||rowspan="5" style="background: #CEE0F2;" |32-bit || [[32-bit computing|32-bit]] [[instruction set architecture|ISA]], paging, [[IBM Personal System/2|IBM PS/2]]
|-
| '''4th''' (pipelining, cache) || 1989 || [[Intel 80486]]<br/>[[Cyrix]] [[Cyrix Cx486SLC|Cx486S]], [[Cyrix Cx486DLC|DLC]] (1992)<br/>[[AMD Am486]] (1993), [[AMD Am5x86|Am5x86]] (1995) || [[Instruction pipelining|pipelining]], on-die [[x87]] [[floating-point unit|FPU]] (486DX), on-die [[CPU cache|cache]]
|-
| rowspan="3" |'''5th'''<br/>([[Superscalar]]) || 1993 || Intel [[P5 (microarchitecture)|Pentium]], [[Pentium MMX]] (1996) || [[Superscalar]], [[64-bit computing|64-bit]] [[Bus (computing)|databus]], faster FPU, [[MMX (instruction set)|MMX]] (Pentium MMX), [[Advanced Programmable Interrupt Controller|APIC]], [[Symmetric multiprocessing|SMP]]
|-
| 1994 || [[NexGen]] Nx586<br/>AMD [[AMD K5|5k86]]/[[AMD K5|K5]] (1996) || Discrete microarchitecture ([[Micro-operation|μ-op]] translation)
|-
| 1995 || [[Cyrix Cx5x86]]<br/>[[Cyrix 6x86]]/MX (1997)/[[Cyrix MII|MII]] (1998) || [[dynamic execution]]
|-
| rowspan="3" |'''6th'''<br/>([[Physical Address Extension|PAE]], μ-op translation)|| 1995 || Intel [[Pentium Pro]] || rowspan="2" style="background: #CEE0F2;" |36-bit ([[Physical Address Extension|PAE]])|| μ-op translation, conditional move instructions, [[dynamic execution]], [[speculative execution]], 3-way x86 superscalar, superscalar FPU, [[Physical Address Extension|PAE]], on-chip [[L2 cache]]
|-
| 1997 ||Intel [[Pentium II]], [[Pentium III]] (1999)<br/>[[Celeron]] (1998), [[Xeon]] (1998) || on-package (Pentium II) or on-die (Celeron) L2 Cache, [[Streaming SIMD Extensions|SSE]] (Pentium III), [[Slot 1]], [[Socket 370]] or [[Slot 2]] (Xeon)
|-
| 1997 || [[AMD K6]]/[[AMD K6-2|K6-2]] (1998)/[[AMD K6-III|K6-III]] (1999)|| style="background: #CEE0F2;" |32-bit ||[[3DNow!]], 3-level cache system (K6-III)
|-
| rowspan="5" |Enhanced Platform|| 1999 || AMD [[Athlon]]<br>[[Athlon XP]]/[[Athlon MP|MP]] (2001)<br/>[[Duron]] (2000)<br>[[Sempron]] (2004) || style="background: #CEE0F2;" |36-bit || MMX+, 3DNow!+, double-pumped bus, [[Slot A]] or [[Socket A]]
|-
| rowspan = "2" |2000 || [[Transmeta Crusoe]] || style="background: #CEE0F2;" |32-bit || [[Code Morphing Software|CMS]] powered x86 platform processor, [[Very long instruction word|VLIW]]-128 core, on-die memory controller, on-die PCI bridge logic
|-
|Intel [[Pentium 4]] || rowspan="3" style="background: #CEE0F2;" |36-bit || [[SSE2]], [[Hyper-Threading|HTT]] (Northwood), NetBurst, quad-pumped bus, Trace Cache, [[Socket 478]]
|-
| rowspan="2" |2003 || Intel [[Pentium M]]<br/>[[Intel Core#Core|Intel Core]] (2006)<br>[[Pentium Dual-Core]] (2007) || [[Micro-op fusion|μ-op fusion]], [[XD bit]] (Dothan) (Intel Core "Yonah")
|-
|[[Transmeta Efficeon]] || [[Code Morphing Software|CMS]] 6.0.4, [[Very long instruction word|VLIW]]-256, [[NX bit]], [[Hyper Transport|HT]]
|-
|style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;" |[[IA-64]]||style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;" |64-bit Transition<br/>1999–2005 || 2001 || Intel [[Itanium]] (2001–2017) || colspan="3" style="background: #ececec;" |52-bit || 64-bit [[Explicitly parallel instruction computing|EPIC]] architecture, 128-bit VLIW instruction bundle, on-die hardware IA-32 H/W enabling x86 OSes & x86 applications (early generations), software IA-32 EL enabling x86 applications (Itanium 2), Itanium register files are remapped to x86 registers
|-
| rowspan="30" style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;" | [[x86-64]] || rowspan="30" style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;" |64-bit Extended<br/>since 2001 || colspan="6" style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;" |x86-64 is the 64-bit extended architecture of x86, its Legacy Mode preserves the entire and unaltered x86 architecture. The native architecture of x86-64 processors: residing in the 64-bit Mode, lacks of access mode in segmentation, presenting 64-bit architectural-permit linear address space; an adapted IA-32 architecture residing in the Compatibility Mode alongside 64-bit Mode is provided to support most x86 applications
|-
| 2003 || [[Athlon 64]]/[[Athlon 64 FX|FX]]/[[Athlon 64 X2|X2]] (2005), [[Opteron]]<br/>[[Sempron]] (2004)/[[Turion 64 X2|X2]] (2008)<br/>[[Turion 64]] (2005)/[[Turion 64 X2|X2]] (2006) || colspan="3" style="background: #ececec;" |40-bit || [[AMD64]] (except some Sempron processors presented as purely x86 processors), on-die memory controller, [[HyperTransport]], on-die dual-core (X2), [[AMD-V]] (Athlon 64 Orleans), [[Socket 754]]/[[Socket 939|939]]/[[Socket 940|940]] or [[Socket AM2|AM2]]
|-
| 2004 || [[Pentium4#Prescott|Pentium 4]] (Prescott)<br/>[[Celeron D]], [[Pentium D]] (2005) ||rowspan="2" colspan="3" style="background: #ececec;" |36-bit || [[EM64T]] (enabled on selected models of Pentium 4 and Celeron D), [[SSE3]], 2nd gen. NetBurst pipelining, dual-core (on-die: Pentium D 8xx, on-chip: Pentium D 9xx), [[Intel VT]] (Pentium 4 6x2), socket [[LGA 775]]
|-
| 2006 || [[Intel Core 2]]<br/>[[Pentium Dual-Core]] (2007)<br/>[[Celeron Dual-Core]] (2008) ||[[Intel 64]] (<<== EM64T), [[SSSE3]] (65&nbsp;nm), wide dynamic execution, μ-op fusion, macro-op fusion in 16-bit and 32-bit mode,<ref name="intel-optimization-for-macro-fusion">{{cite web|url=https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf|title=Intel 64 and IA-32 Architectures Optimization Reference Manual|at=3.4.2.2 Optimizing for Macro-fusion|date=September 2019|publisher=Intel|access-date=March 7, 2020|archive-date=February 14, 2020|archive-url=https://web.archive.org/web/20200214191947/https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf|url-status=live}}</ref><ref name="agner-fog-microarchitecture">{{cite web|url=https://www.agner.org/optimize/microarchitecture.pdf|title=The microarchitecture of Intel, AMD and VIA CPUs|last=Fog|first=Agner|page=107|quote=Core2 can do macro-op fusion only in 16-bit and 32-bit mode. Core Nehalem can also do this in 64-bit mode.|access-date=March 7, 2020|archive-date=March 22, 2019|archive-url=https://web.archive.org/web/20190322145155/https://www.agner.org/optimize/microarchitecture.pdf|url-status=live}}</ref> on-chip quad-core(Core 2 Quad), Smart Shared L2 Cache (Intel Core 2 "Merom")
|-
| 2007 || [[AMD Phenom]]/[[AMD Phenom II|II]] (2008)<br/>[[AMD Athlon II|Athlon II]] (2009)<br>[[AMD Turion#Turion II|Turion II]] (2009)|| colspan="3" style="background: #ececec;" |48-bit || Monolithic quad-core (X4)/triple-core (X3), [[SSE4a]], [[Rapid Virtualization Indexing]] (RVI), HyperTransport 3, [[AM2+]] or [[AM3]]
|-
| rowspan="4" |2008 || [[Intel Core 2]] (45&nbsp;nm) ||rowspan = "4" colspan="3" style="background: #ececec;" |40-bit || [[SSE4.1]]
|-
| [[Intel Atom]] || netbook or low power smart device processor, P54C core reused
|-
| Intel [[Core i7]]<br/>[[Core i5]] (2009)<br>[[Intel Core i3|Core i3]] (2010)|| QuickPath, on-chip GMCH ([[Clarkdale (microprocessor)|Clarkdale]]), [[SSE4|SSE4.2]], [[Second Level Address Translation#Extended Page Tables|Extended Page Tables]] (EPT) for virtualization, macro-op fusion in 64-bit mode,<ref name="intel-optimization-for-macro-fusion"/><ref name="agner-fog-microarchitecture"/> (Intel Xeon "Bloomfield" with Nehalem microarchitecture)

|-
| [[VIA Nano]] || [[hardware-based encryption]]; adaptive [[power management]]
|-
| 2010 ||[[Bulldozer (microarchitecture)|AMD FX]] || colspan="3" style="background: #ececec;" |48-bit || octa-core, CMT(Clustered Multi-Thread), FMA, OpenCL, AM3+
|-
| rowspan="3" |2011 || AMD APU A and E Series ([[AMD Accelerated Processing Unit|Llano]]) || colspan="3" style="background: #ececec;" |40-bit || on-die GPGPU, PCI Express 2.0, [[Socket FM1]]
|-
| AMD APU C, E and Z Series ([[Bobcat (processor)|Bobcat]]) || rowspan = "2" colspan="3" style="background: #ececec;" |36-bit || low power smart device APU
|-
| [[Intel Core i3]], [[Core i5]] and [[Core i7]]<br/>([[Sandy Bridge (microarchitecture)|Sandy Bridge]]/[[Ivy Bridge (microarchitecture)|Ivy Bridge]]) || Internal Ring connection, decoded μ-op cache, [[LGA 1155]] socket
|-
| rowspan = "2" |2012 || AMD APU A Series ([[Bulldozer (processor)|Bulldozer, Trinity]] and later) || rowspan = "3" colspan="3" style="background: #ececec;" |48-bit || [[Advanced Vector Extensions|AVX]], Bulldozer based APU, [[Socket FM2]] or [[Socket FM2+]]
|-
| Intel [[Xeon Phi]] ([[Knights Corner]]) || PCI-E add-on card coprocessor for XEON based system, Manycore Chip, In-order [[P5 (microarchitecture)|P54C]], very wide VPU (512-bit SSE), LRBni instructions (8× 64-bit)
|-
| rowspan = "3" |2013 || |AMD [[Jaguar (microarchitecture)|Jaguar]]<br/>(Athlon, Sempron) || [[System on a chip|SoC]], game console and low power smart device processor
|-
| Intel [[Silvermont]]<br/>(Atom, Celeron, Pentium) ||colspan="3" style="background: #ececec;" |36-bit || [[System on a chip|SoC]], low/ultra-low power smart device processor
|-
|[[Intel Core i3]], [[Core i5]] and [[Core i7]] ([[Haswell (microarchitecture)|Haswell]]/[[Broadwell (microarchitecture)|Broadwell]]) || rowspan = "2" colspan="3" style="background: #ececec;" |39-bit || [[Advanced Vector Extensions 2|AVX2]], [[FMA instruction set|FMA3]], [[Transactional Synchronization Extensions|TSX]], [[Bit Manipulation Instruction Sets|BMI1, and BMI2]] instructions, [[LGA 1150]] socket
|-
| 2015 || Intel [[Broadwell (microarchitecture)|Broadwell-U]]<br/>([[Intel Core i3]], [[Core i5]], [[Core i7]], [[List of Intel Core M microprocessors|Core M]], [[Pentium]], [[Celeron]]) || SoC, on-chip Broadwell-U PCH-LP (Multi-chip module)
|-
|2015–2020 || Intel [[Skylake (microarchitecture)|Skylake]]/[[Kaby Lake]]/[[Cannon Lake (microarchitecture)|Cannon Lake]]/[[Coffee Lake (microarchitecture)|Coffee Lake]]/[[Rocket Lake (microarchitecture)|Rocket Lake]]<br/>(Intel Pentium/Celeron Gold, [[Core i3]], [[Core i5]], [[Core i7]], [[Core i9]]) || colspan="3" style="background: #ececec;" |46-bit || AVX-512 (restricted to Cannon Lake-U and workstation/server variants of Skylake)
|-
| 2016 || Intel [[Xeon Phi]] ([[Knights Landing (microarchitecture)|Knights Landing]]) || colspan="3" rowspan="4" style="background: #ececec" | 48-bit || Manycore CPU and coprocessor for Xeon systems, Airmont (Atom) based core
|-
|2016 || AMD [[Bristol Ridge]]<br/>(AMD (Pro) A6/A8/A10/A12) || Integrated FCH on die, SoC, AM4 socket
|-
|2017 || AMD [[Ryzen]] Series/AMD [[Epyc]] Series || AMD's implementation of SMT, on-chip multiple dies
|-
|2017 || Zhaoxin WuDaoKou (KX-5000, KH-20000) || [[Zhaoxin]]'s first brand new x86-64 architecture
|-
|2018–2021 || Intel [[Sunny Cove (microarchitecture)|Sunny Cove]] ([[Ice Lake (microprocessor)|Ice Lake]]-U and Y), [[Cypress Cove (microarchitecture)|Cypress Cove]] ([[Rocket Lake]]) || colspan="3" style="background: #ececec;" |57-bit || Intel's first implementation of AVX-512 for the consumer segment. Addition of Vector Neural Network Instructions (VNNI)
|-
|2019
|AMD [[AMD Matisse|Matisse]]
| colspan="3" style="background: #ececec" |48-bit
|Multiple Chip Module design with I/O die separate from CPU die(s), Support for PCIe Gen4
|-
|2020 || Intel [[Willow Cove]] ([[Tiger Lake]]-Y/U/H) 
| colspan="3" rowspan="2" style="background: #ececec" |57-bit|| Dual ring interconnect architecture, updated Gaussian Neural Accelerator (GNA2), new AVX-512 Vector Intersection Instructions, addition of Control-Flow Enforcement Technology (CET)
|-
|2021 || Intel [[Alder Lake (microarchitecture)|Alder Lake]] || Hybrid design with performance (Golden Cove) and efficiency cores (Gracemont), support for PCIe Gen5 and DDR5, updated Gaussian Neural Accelerator (GNA3). AVX-512 not officially supported
|-
|2022
|AMD [[AMD Vermeer|Vermeer]] (5800X3D)
| colspan="3" rowspan="2" style="background: #ececec" |48-bit
|X3D chips have an additional 64MB 3D vertically stacked L3 cache (3D V-Cache) for up to 96MB L3 Cache
|-
|2022
|AMD [[AMD Raphael|Raphael]]
|AMD's first implementation of AVX-512 for the consumer segment, iGPU now standard on Ryzen CPU's with 2 [[RDNA 2]] compute cores
|}