Editing XAUI (section)

== RXAUI ==
'''Reduced  Pin eXtended Attachment Unit Interface''' ('''RXAUI''') is a proprietary modification created by [[Marvell Technology|Marvell]]<ref name=marvell>Marvell MV-S 105386-00 RXAUI Interface and RXAUI Adapter Specifications</ref> and Dune Networks<ref name=dune>Dune Networks DN-DS-RXAUI-Spec v1.0, RXAUI - Reduced Pin XAUI</ref> (later acquired by [[Broadcom Corporation|Broadcom]]<ref>[https://venturebeat.com/2009/11/30/broadcom-buys-dune-networks-for-178m-to-make-insanely-fast-networking-chips/ Broadcom buys Dune Networks for $178M to make insanely fast networking chips]</ref>) aimed to increase the port density by decreasing the interface pin count. The four lanes of the standard XAUI running at 3.125&nbsp;Gbit/s are replaced by two lanes at 6.25&nbsp;Gbit/s. Thus 16 pins of an integrated circuit (4 transmit + 4 receive differential pairs) can provide either one XAUI port or two RXAUI ports.

The specification also defines a XAUI to RXAUI adapter and provides an implementation as [[Verilog]] RTL code.<ref name=marvell /> [[FPGA]] vendors are offering their own implementations as IP blocks.<ref name=xilinx>Xilinx, [https://www.xilinx.com/support/documentation/ip_documentation/rxaui_ds740.pdf LogiCORE IP RXAUI v2.1]</ref><ref name=altera>Altera, [https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/products/ip/ampp/morethanip/documents/m-mtip-10_gigabit_xgxs_pcs.pdf 10 Gigabit Reduced XAUI PCS Core Product Brief]</ref>