Editing Zero page (section)

== Computers with few CPU registers ==
In early computers, such as the [[PDP-8]], the zero page had a special fast [[addressing mode]], which facilitated its use for temporary [[computer storage|storage of data]] and compensated for the paucity of [[central processing unit|CPU]] [[processor register|register]]s.  The PDP-8 had only one register, so zero page addressing was essential.  In the original [[PDP-10#Registers|PDP-10]] KA-10 models, the available registers are simply the first 16 words, [[36-bit computing|36-bits]] long, of main memory.  Those locations can be accessed as both registers and memory locations.

Unlike more modern hardware, 1970s-era computer [[random-access memory|RAM]] was as fast as the CPU.  Thus, it made sense to have few registers and use the main memory as an extended pool of extra registers.  In machines with a [[16-bit]] [[address bus]] and [[8-bit]] [[bus (computing)|data bus]], accessing zero page locations could be faster than accessing other locations.  Since zero page locations could be addressed by a single [[byte]], the instructions accessing them could be shorter and hence faster-loading.

{{anchor|Direct addressing|Zero-page addressing}}For example, the [[MOS Technology 6502]] family has only one general purpose register: the accumulator.  To offset this limitation and gain a performance advantage, the 6502 is designed to make special use of the zero page, providing instructions whose [[operand]]s are eight bits, instead of 16, thus requiring fewer memory fetch cycles.  Many [[instruction set architecture|instructions]] are coded differently for zero page and non-zero page addresses; this is called ''zero-page addressing'' in 6502 terminology (it is called ''direct addressing'' in [[Motorola 6800]] terminology; the [[Western Design Center]] [[65C816]] also refers to zero page addressing as ''direct page addressing''):
<syntaxhighlight lang="nasm">
 LDA $12            ; zero page addressing
 LDA $0012          ; absolute addressing
</syntaxhighlight>

In 6502 assembly language, the above two instructions both accomplish the same thing: they load the value of memory location <code>$12</code> into the <code>.A</code> (accumulator) register (<code>$</code> is Motorola/MOS Technology assembly language notation for a hexadecimal number).  However, the first instruction is only two bytes long and requires three clock cycles to complete.  The second instruction is three bytes in length and requires four clock cycles to execute.  This difference in execution time could become significant in repetitive code.

{{anchor|Direct page|Direct page addressing}}Some processors, such as the [[Motorola 6809]] and the aforementioned WDC 65C816, implement a “direct page register” (<code>DP</code>) that tells the processor the starting address in [[RAM]] of what is considered to be zero page.  In this context, zero page addressing is notional; the actual access would not be to the physical zero page if <code>DP</code> is loaded with some address other than <code>$00</code> (or <code>$0000</code> in the case of the 65C816).